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SPC58EEX 数据表(PDF) 11 Page - STMicroelectronics |
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SPC58EEX 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 154 page ![]() DS11646 Rev 4 11/154 SPC58EEx, SPC58NEx Introduction 12 1.5 Features On-chip modules within SPC58xEx include the following features: • main CPUs, dual issue, 32-bit CPU core complexes (e200z4), paired in lock-step. – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction – Single-precision floating point operations – Lightweight signal processing auxiliary processing unit (LSP APU) instruction support for digital signal processing (DSP) on Core_2 – 16 KB Local instruction RAM and 64 KB local data RAM for Core_0 and Core_1, 16 KB Local instruction RAM and 32 KB local data RAM for Core_2 – 8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_1, 8kB I-Cache for Core_2 • 6582 KB on-chip Flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation – Supports read while read between the two code Flash partitions. • 608 KB on-chip general-purpose SRAM (+ 160 KB data RAM included in the CPUs) • Multi channel direct memory access controllers (eDMA paired in lock-step) – One eDMA with 64 channels – One eDMA with 32 channels • One interrupt controller (INTC) in lock-step • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell • Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC • Hardware security module (HSM) to provide robust integrity checking of Flash memory • System integration unit lite (SIUL) • Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART. • GTM343 - generic timer module – Intelligent complex timer module – 144 channels (40 input and 104 output) – 5 programmable fine grain multi-threaded cores – 61 KB of dedicated RAM – 24-bit wide channels – Hardware support for engine control, motor control and safety related applications • Enhanced analog-to-digital converter system with – One supervisor 12-bit SAR analog converter – Four separate fast 12-bit SAR analog converters – Three separate 10-bit SAR analog converters, one with STDBY mode support (except in eLQFP176 package) – Six separate 16-bit Sigma-Delta analog converters • Ten deserial serial peripheral interface (DSPI) modules |
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