STM32F373VC datasheet(101/137 Pages) STMICROELECTRONICS

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DocID022691 Rev 7

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STM32F373xx

Electrical characteristics

114

6.3.18

DAC electrical specifications

Table 63. DAC characteristics

Symbol

Parameter

Conditions

Min Typ

Max

Unit

VDDA

Analog supply voltage

2.4

3.6

VREF+

Reference supply voltage VREF+ must always be below VDDA

2.4

3.6

VSSA

Ground

RLOAD(1)

Resistive load

DAC

output

buffer ON

Connected to VSSA

Connected to VDDA

RO(1)

Output Impedance

DAC output buffer OFF

CLOAD(1)

Capacitive load

Maximum capacitive load at DAC_OUT

pin (when the buffer is ON).

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer ON

It gives the maximum output excursion

of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at VREF+ = 3.6 V

and (0x155) and (0xEAB) at VREF+ =

2.4 V

0.2

DAC_OUT

max(1)

Higher DAC_OUT

voltage with buffer ON

VDDA – 0.2

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer OFF

It gives the maximum output excursion

of the DAC.

-0.5

DAC_OUT

max(1)

Higher DAC_OUT

voltage with buffer OFF

VREF+ – 1LSB

IDDVREF+(3)

DAC DC current

consumption in quiescent

mode (Standby mode)

With no load, worst code (0xF1C) at

VREF+ = 3.6 V in terms of DC

consumption on the inputs

220

µA

IDDA(3)

DAC DC current

consumption in quiescent

mode(2)

With no load, middle code (0x800) on

the inputs

380

µA

With no load, worst code (0xF1C) at

VREF+ = 3.6 V in terms of DC

consumption on the inputs

480

µA

DNL(3)

Differential non linearity

Difference between two

consecutive code-1LSB)

Given for the DAC in 10-bit

configuration

± 0.5

LSB

Given for the DAC in 12-bit

configuration

± 2

LSB

INL(3)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i

on a line drawn between

Code 0 and last Code

1023)

Given for the DAC in 10-bit

configuration

± 1

LSB

Given for the DAC in 12-bit

configuration

± 4

LSB

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