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ADE7933 数据表(PDF) 111 Page - Analog Devices

部件名 ADE7933
功能描述  Isolated Energy Metering Chipset for Polyphase Shunt Meters
PDF  125 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7933 数据表(HTML) 111 Page - Analog Devices

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Data Sheet
ADE7978/ADE7933/ADE7932/ADE7923
Rev. D | Page 111 of 125
Address
Register
Name
R/W1
Bit
Length
Bit Length During
Communication2
Type3
Default
Value4
Description
0xE909
VARNOLOAD
R/W
16
16
U
0x0000
No load threshold in the total/fundamental
reactive power datapath.
0xE90A
VANOLOAD
R/W
16
16
U
0x0000
No load threshold in the apparent power
datapath.
0xE90B
to
0xE9FD
Reserved
These addresses should not be written for
proper operation.
0xE9FE
LAST_ADD
R
16
16
U
N/A
Contains the address of the register accessed
during the last successful read or write
operation.
0xE9FF
LAST_
RWDATA16
R
16
16
U
N/A
Contains the data from the last successful
16-bit register communication.
0xEA00
CONFIG2
R/W
8
8
U
0x00
Configuration register (see Table 62).
0xEA01
LAST_OP
R
8
8
U
N/A
Indicates the type (read or write) of the last
successful read or write operation.
0xEA02
WTHR
R/W
8
8
U
0x03
Threshold used in phase total/fundamental
active energy datapath.
0xEA03
VARTHR
R/W
8
8
U
0x03
Threshold used in phase total/fundamental
reactive energy datapath.
0xEA04
VATHR
R/W
8
8
U
0x03
Threshold used in phase apparent energy
datapath.
0xEA05
to
0xEBFE
Reserved
8
8
These addresses should not be written for
proper operation.
0xEBFF
Reserved
8
8
This address can be used to manipulate the
SS/HSA pin when SPI is chosen as the active
port. See the Serial Interfaces section for
more information.
1 R = read only; R/W = read and write.
2 32 ZP = 24-bit signed or unsigned register that is transmitted as a 32-bit word with eight MSBs padded with 0s. 32 SE = 24-bit signed register that is transmitted as a
32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3 U = unsigned register; S = signed register in twos complement format.
4 N/A = not applicable.
Table 43. IPEAK Register (Address 0xE500)
Bits
Bit Name
Default Value
Description
[23:0]
IPEAKVAL[23:0]
0
These bits contain the peak value determined in the current channel.
24
IPPHASE[0]
0
When this bit is set to 1, the Phase A current generated the IPEAKVAL[23:0] value.
25
IPPHASE[1]
0
When this bit is set to 1, the Phase B current generated the IPEAKVAL[23:0] value.
26
IPPHASE[2]
0
When this bit is set to 1, the Phase C current generated the IPEAKVAL[23:0] value.
[31:27]
00000
These bits are always set to 0.
Table 44. VPEAK Register (Address 0xE501)
Bits
Bit Name
Default Value
Description
[23:0]
VPEAKVAL[23:0]
0
These bits contain the peak value determined in the voltage channel.
24
VPPHASE[0]
0
When this bit is set to 1, the Phase A voltage generated the VPEAKVAL[23:0] value.
25
VPPHASE[1]
0
When this bit is set to 1, the Phase B voltage generated the VPEAKVAL[23:0] value.
26
VPPHASE[2]
0
When this bit is set to 1, the Phase C voltage generated the VPEAKVAL[23:0] value.
[31:27]
00000
These bits are always set to 0.



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