ADE7933 datasheet(112/125 Pages) AD

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ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 112 of 125

Table 45. STATUS0 Register (Address 0xE502)

Bits

Bit Name

Default Value

Description

AEHF

When this bit is set to 1, it indicates that Bit 30 in one of the total active energy registers

(AWATTHR, BWATTHR, or CWATTHR) has changed.

FAEHF

When this bit is set to 1, it indicates that Bit 30 in one of the fundamental active energy

registers (FWATTHR, BFWATTHR, or CFWATTHR) has changed.

REHF

When this bit is set to 1, it indicates that Bit 30 in one of the total reactive energy registers

(AVARHR, BVARHR, or CVARHR) has changed.

FREHF

When this bit is set to 1, it indicates that Bit 30 in one of the fundamental reactive energy

registers (AFVARHR, BFVARHR, or CFVARHR) has changed.

VAEHF

When this bit is set to 1, it indicates that Bit 30 in one of the apparent energy registers

(AVAHR, BVAHR, or CVAHR) has changed.

LENERGY

When this bit is set to 1, it indicates the end of an integration over the integer number of

half line cycles set in the LINECYC register (line cycle energy accumulation mode).

REVAPA

When this bit is set to 1, it indicates that the Phase A active power (total or fundamental)

identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 54).

REVAPB

When this bit is set to 1, it indicates that the Phase B active power (total or fundamental)

identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 54).

REVAPC

When this bit is set to 1, it indicates that the Phase C active power (total or fundamental)

identified by Bit 0 (REVAPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 54).

REVPSUM1

When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath

has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register

(see Table 54).

REVRPA

When this bit is set to 1, it indicates that the Phase A reactive power (total or fundamental)

identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 4 (AVARSIGN) of the PHSIGN register (see Table 54).

REVRPB

When this bit is set to 1, it indicates that the Phase B reactive power (total or fundamental)

identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 5 (BVARSIGN) of the PHSIGN register (see Table 54).

REVRPC

When this bit is set to 1, it indicates that the Phase C reactive power (total or fundamental)

identified by Bit 1 (REVRPSEL) in the MMODE register has changed sign. The sign itself is

indicated in Bit 6 (CVARSIGN) of the PHSIGN register (see Table 54).

REVPSUM2

When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath

has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN register

(see Table 54).

CF1

When this bit is set to 1, it indicates that a high to low transition has occurred at the CF1

pin; that is, an active low pulse has been generated. This bit is set even if the CF1 output is

disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at

the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 52).

CF2

When this bit is set to 1, it indicates that a high to low transition has occurred at the CF2

pin; that is, an active low pulse has been generated. This bit is set even if the CF2 output is

disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at

the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 52).

CF3

When this bit is set to 1, it indicates that a high to low transition has occurred at the CF3

pin; that is, an active low pulse has been generated. This bit is set even if the CF3 output is

disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at

the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 52).

DREADY

When this bit is set to 1, it indicates that all periodical (8 kHz rate) DSP computations have

finished.

REVPSUM3

When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath

has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN register

(see Table 54).

[31:19]

Reserved

0 0000 0000

0000

Reserved. These bits are always set to 0.

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