ADE7933 datasheet(117/125 Pages) AD

117 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 117 of 125

Table 51. COMPMODE Register (Address 0xE60E)

Bits

Bit Name

Default Value

Description

TERMSEL1[0]

0: Phase A is not included in the CF1 output calculations.

1: Phase A is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111

specifies that the sum of all three phases is included in the CF1 output.

TERMSEL1[1]

0: Phase B is not included in the CF1 output calculations.

1: Phase B is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111

specifies that the sum of all three phases is included in the CF1 output.

TERMSEL1[2]

0: Phase C is not included in the CF1 output calculations.

1: Phase C is included in the CF1 output calculations. Setting the TERMSEL1[2:0] bits to 111

specifies that the sum of all three phases is included in the CF1 output.

TERMSEL2[0]

0: Phase A is not included in the CF2 output calculations.

1: Phase A is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111

specifies that the sum of all three phases is included in the CF2 output.

TERMSEL2[1]

0: Phase B is not included in the CF2 output calculations.

1: Phase B is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111

specifies that the sum of all three phases is included in the CF2 output.

TERMSEL2[2]

0: Phase C is not included in the CF2 output calculations.

1: Phase C is included in the CF2 output calculations. Setting the TERMSEL2[2:0] bits to 111

specifies that the sum of all three phases is included in the CF2 output.

TERMSEL3[0]

0: Phase A is not included in the CF3 output calculations.

1: Phase A is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111

specifies that the sum of all three phases is included in the CF3 output.

TERMSEL3[1]

0: Phase B is not included in the CF3 output calculations.

1: Phase B is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111

specifies that the sum of all three phases is included in the CF3 output.

TERMSEL3[2]

0: Phase C is not included in the CF3 output calculations.

1: Phase C is included in the CF3 output calculations. Setting the TERMSEL3[2:0] bits to 111

specifies that the sum of all three phases is included in the CF3 output.

[10:9]

ANGLESEL[1:0]

00: delays between the voltages and currents of the same phase are measured.

01: delays between the phase voltages are measured.

10: delays between the phase currents are measured.

11: no delays are measured.

VNOMAEN

0: the apparent power on Phase A is computed normally by multiplying the voltage rms

value by the current rms value.

1: the apparent power on Phase A is computed by multiplying the phase rms current by an

rms voltage written to the VNOM register (Address 0xE533).

VNOMBEN

0: the apparent power on Phase B is computed normally by multiplying the voltage rms

value by the current rms value.

1: the apparent power on Phase B is computed by multiplying the phase rms current by an

rms voltage written to the VNOM register (Address 0xE533).

VNOMCEN

0: the apparent power on Phase C is computed normally by multiplying the voltage rms

value by the current rms value.

1: the apparent power on Phase C is computed by multiplying the phase rms current by an

rms voltage written to the VNOM register (Address 0xE533).

SELFREQ

0: ADE7978 is connected to a 50 Hz network.

1: ADE7978 is connected to a 60 Hz network.

Reserved

This bit is set to 0 by default and does not manage any functionality.

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