ADE7933 datasheet(120/125 Pages) AD

120 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 120 of 125

Table 55. CONFIG Register (Address 0xE618)

Bits

Bit Name

Default Value

Description

[1:0]

ZX_DREADY

This bit manages the output signal at the ZX/DREADY pin. For more information about the

zero-crossing function, see the Zero-Crossing Detection section.

00: DREADY functionality is enabled (see the Digital Signal Processor section).

01: ZX functionality is generated by the Phase A voltage.

10: ZX functionality is generated by the Phase B voltage.

11: ZX functionality is generated by the Phase C voltage.

Reserved

Reserved. This bit is always set to 0.

Swap

1: the voltage channel outputs VA, VB, VC, and VN are swapped with the current channel

outputs IA, IB, IC, and IN, respectively. Thus, the current channel information is present in

the phase voltage channel registers and vice versa.

HPFEN

0: all high-pass filters in the voltage and current channels are disabled.

1: all high-pass filters in the voltage and current channels are enabled.

LPFSEL

This bit specifies the settling time introduced by the low-pass filter in the total active

power datapath.

0: settling time = 650 ms.

1: settling time = 1300 ms.

HSDCEN

0: HSDC serial port is disabled and CF3 functionality is configured on the CF3/HSCLK pin.

1: HSDC serial port is enabled and HSCLK functionality is configured on the CF3/HSCLK pin.

SWRST

When this bit is set to 1, a software reset is initiated.

[9:8]

VTOIA[1:0]

These bits select the phase voltage that is considered together with the Phase A current in

the power path.

00: Phase A voltage.

01: Phase B voltage.

10: Phase C voltage.

11: reserved (same as VTOIA[1:0] = 00).

[11:10]

VTOIB[1:0]

These bits select the phase voltage that is considered together with the Phase B current in

the power path.

00: Phase B voltage.

01: Phase C voltage.

10: Phase A voltage.

11: reserved (same as VTOIB[1:0] = 00).

[13:12]

VTOIC[1:0]

These bits select the phase voltage that is considered together with the Phase C current in

the power path.

00: Phase C voltage.

01: Phase A voltage.

10: Phase B voltage.

11: reserved (same as VTOIC[1:0] = 00).

INSEL

0: the NIRMS register (Address 0x43C9) contains the rms value of the neutral current.

1: the NIRMS register contains the rms value of ISUM, the instantaneous value of the sum

of all three phase currents, IA, IB, and IC.

Reserved

Reserved. This bit does not manage any functionality.

ADE7933 数据表(PDF) 120 Page - Analog Devices

ADE7933 数据表(HTML) 120 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7933 数据表(PDF) 120 Page - Analog Devices

ADE7933 数据表(HTML) 120 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载