ADE7933 datasheet(123/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 123 of 125

Table 60. HSDC_CFG Register (Address 0xE706)

Bits

Bit Name

Default Value

Description

HCLK

0: HSCLK is 8 MHz.

1: HSCLK is 4 MHz.

HSIZE

0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.

1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.

HGAP

0: no gap is introduced between packages.

1: a gap of seven HCLK cycles is introduced between packages.

[4:3]

HXFER[1:0]

00: HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,

VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.

01: HSDC transmits seven instantaneous values of currents and voltages in the following order:

IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and INWV.

10: HSDC transmits nine instantaneous values of phase powers in the following order:

AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.

11: reserved (same as HXFER[1:0] = 00).

HSAPOL

0: SS/HSA output pin is active low.

1: SS/HSA output pin is active high.

[7:6]

Reserved

Reserved. These bits do not manage any functionality.

Table 61. CONFIG3 Register (Address 0xE708)

Bits

Bit Name

DefaultValue

Description

VA2_EN

This bit configures the V2 channel or temperature measurement on the Phase A ADE7933/ADE7932.

0: temperature sensor is measured on the second voltage channel of the Phase A ADE7933/ADE7932.

On the ADE7932, the temperature sensor is always sensed by the second voltage channel, but this bit

must still be cleared to 0 to enable the temperature measurement.

1: V2P input is sensed on the second voltage channel of the Phase A ADE7933.

VB2_EN

This bit configures the V2 channel or temperature measurement on the Phase B ADE7933/ADE7932.

0: temperature sensor is measured on the second voltage channel of the Phase B ADE7933/ADE7932.

On the ADE7932, the temperature sensor is always sensed by the second voltage channel, but this bit

must still be cleared to 0 to enable the temperature measurement.

1: V2P input is sensed on the second voltage channel of the Phase B ADE7933.

VC2_EN

This bit configures the V2 channel or temperature measurement on the Phase C ADE7933/ADE7932.

0: temperature sensor is measured on the second voltage channel of the Phase C ADE7933/ADE7932.

On the ADE7932, the temperature sensor is always sensed by the second voltage channel, but this bit

must still be cleared to 0 to enable the temperature measurement.

1: V2P input is sensed on the second voltage channel of the Phase C ADE7933.

VN2_EN

This bit configures the V2 channel or temperature measurement on the neutral line ADE7923 or

ADE7933/ADE7932.

0: temperature sensor is measured on the second voltage channel of the neutral line ADE7933/

ADE7932 and ADE7923. On the ADE7932, the temperature sensor is always sensed by the second

voltage channel, but this bit must still be cleared to 0 to enable the temperature measurement.

1: V2P input is sensed on the second voltage channel of the neutral line ADE7933 and ADE7923.

[5:4]

Reserved

Reserved. These bits do not manage any functionality.

CLKOUT_DIS

0: ADE7933/ADE7932 and ADE7923 CLKOUT pins are enabled.

1: ADE7933/ADE7932 and ADE7923 CLKOUT pins are set high and no clock is generated.

ADE7933_

SWRST

When this bit is set to 1, a software reset of the ADE7933/ADE7932 and ADE7923 devices is initiated.

See the ADE7933/ADE7932 and ADE7923 Software Reset section for more information.

Table 62. CONFIG2 Register (Address 0xEA00)

Bits

Bit Name

DefaultValue

Description

I2C_LOCK

When this bit is set to 0, the SS/HSA pin can be toggled three times to activate the SPI serial port. If

I2C is the selected serial port, set this bit to 1 to lock the selection. After a 1 is written to this bit, the

ADE7978 ignores spurious toggling of the SS/HSA pin. If SPI is the selected serial port, any write to

the CONFIG2 register locks the selection. The communication protocol can be changed only after a

power-down or hardware reset operation.

[7:1]

Reserved

000 0000

Reserved. These bits do not manage any functionality.

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