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DVR 数据表(PDF) 194 Page - Microchip Technology |
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DVR 数据表(HTML) 194 Page - Microchip Technology |
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194 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 194 2016-2018 Microchip Technology Inc. TABLE 16-6: AUTO-SHUTDOWN SOURCES REGISTER 16-3: CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 PWMRSEN ASDGM — SSDG — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASDG7 ASDG6 ASDG5 ASDG4 ASDG3 ASDG2 ASDG1 ASDG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMRSEN: CCPx PWM Restart Enable bit 1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended 0 = ASEVT bit must be cleared in software to resume PWM activity on output pins bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit 1 = Waits until the next Time Base Reset or rollover for shutdown to occur 0 = Shutdown event occurs immediately bit 13 Unimplemented: Read as ‘0’ bit 12 SSDG: CCPx Software Shutdown/Gate Control bit 1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM bit still applies) 0 = Normal module operation bit 11-8 Unimplemented: Read as ‘0’ bit 7-0 ASDG<7:0>: CCPx Auto-Shutdown/Gating Source Enable bits 1 = ASDGx Source n is enabled (see Table 16-6 for auto-shutdown/gating sources) 0 = ASDGx Source n is disabled ASDG<7:0> Auto-Shutdown Source MCCP1 MCCP2 MCCP3 MCCP4 1xxx xxxx OCFB x1xx xxxx OCFA xx1x xxxx CLC1 CLC2 Not Used xxx1 xxxx Not Used xxxx 1xxx Not Used xxxx x1xx CMP3 Out xxxx xx1x CMP2 Out xxxx xxx1 CMP1 Out |
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