DVR datasheet(224/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 224

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I2CxCONL: I2Cx CONTROL REGISTER LOW

R/W-0

U-0

HC/R/W-0

R/W-1

R/W-0

I2CEN

—

I2CSIDL

SCLREL(1)

STRICT

A10M

DISSLW

SMEN

bit 15

bit 8

R/W-0

HC/R/W-0

GCEN

STREN

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

I2CEN: I2Cx Enable bit (writable from software only)

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0 = Disables the I2Cx module; all I2C pins are controlled by port functions

bit 14

Unimplemented: Read as ‘0’

bit 13

I2CSIDL: I2Cx Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (I2C Slave mode only)(1)

Module resets and (I2CEN = 0) sets SCLREL = 1.

If STREN = 0:(2)

1 = Releases clock

0 = Forces clock low (clock stretch)

If STREN = 1:

1 = Releases clock

0 = Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCLx low

bit 11

STRICT: I2Cx Strict Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced (for reserved addresses, refer to Table 18-2)

In Slave Mode: The device doesn’t respond to reserved address space and addresses falling in

that category are NACKed.

In Master Mode: The device is allowed to generate addresses with reserved address space.

0 = Reserved addressing would be Acknowledged

In Slave Mode: The device will respond to an address falling in the reserved address space. When

there is a match with any of the reserved addresses, the device will generate an ACK.

In Master Mode: Reserved.

bit 10

A10M: 10-Bit Slave Address Flag bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9

DISSLW: Slew Rate Control Disable bit

1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)

0 = Slew rate control is enabled for High-Speed mode (400 kHz)

Note 1:

Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end

of slave reception. The user software must provide a delay between writing to the transmit buffer and set-

ting the SCLREL bit. This delay must be greater than the minimum setup time for slave transmissions, as

specified in Section 32.0 “Electrical Characteristics”.

Automatically cleared to ‘0’ at the beginning of slave transmission.

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