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DVR 数据表(PDF) 283 Page - Microchip Technology |
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DVR 数据表(HTML) 283 Page - Microchip Technology |
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283 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 283 PIC24FJ256GA705 FAMILY TABLE 23-1: MODULE-SPECIFIC INPUT DATA SOURCES Bit Field Value Input Source CLC1 CLC2 DS4<2:0> 011 SDI1 SDI2 001 CLC2 Output CLC1 Output DS3<2:0> 100 U1RX U2RX 011 SDO1 SDO2 001 CLC1 Output CLC2 Output DS2<2:0> 011 U1TX U2TX 001 CLC2 Output CLC1 Output REGISTER 23-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 G2D4T: Gate 2 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 2 0 = The Data Source 4 signal is disabled for Gate 2 bit 14 G2D4N: Gate 2 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 2 0 = The Data Source 4 inverted signal is disabled for Gate 2 bit 13 G2D3T: Gate 2 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 2 0 = The Data Source 3 signal is disabled for Gate 2 bit 12 G2D3N: Gate 2 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 2 0 = The Data Source 3 inverted signal is disabled for Gate 2 bit 11 G2D2T: Gate 2 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 2 0 = The Data Source 2 signal is disabled for Gate 2 bit 10 G2D2N: Gate 2 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 2 0 = The Data Source 2 inverted signal is disabled for Gate 2 bit 9 G2D1T: Gate 2 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 2 0 = The Data Source 1 signal is disabled for Gate 2 |
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