DVR datasheet(106/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 106

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9.4

Clock Switching Operation

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

9.4.1

ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration

bit in FOSC must be programmed to ‘0’. (Refer to

Section 29.1 “Configuration Bits” for further details.)

If the FCKSM1 Configuration bit is unprogrammed (‘1’),

the clock switching function and Fail-Safe Clock

Monitor function are disabled; this is the default setting.

The NOSCx control bits (OSCCON<10:8>) do not control

the clock selection when clock switching is disabled.

However, the COSC<2:0> bits (OSCCON<14:12>) will

reflect the clock source selected by the FNOSCx

Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

9.4.2

OSCILLATOR SWITCHING

SEQUENCE

At a minimum, performing a clock switch requires this

basic sequence:

desired,

read

the

COSCx

bits

(OSCCON<14:12>) to determine the current

oscillator source.

Perform the unlock sequence to allow a write to

the OSCCON register high byte.

Write the appropriate value to the NOSCx bits

(OSCCON<10:8>) for the new oscillator source.

Perform the unlock sequence to allow a write to

the OSCCON register low byte.

Set the OSWEN bit to initiate the oscillator

switch.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

The clock switching hardware compares the

COSCx bits with the new value of the NOSCx

bits. If they are the same, then the clock switch

is a redundant operation. In this case, the

OSWEN bit is cleared automatically and the

clock switch is aborted.

If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

bits are cleared.

The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

The hardware waits for ten clock cycles from the

new clock source and then performs the clock

switch.

The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSCx

bits value is transferred to the COSCx bits.

The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM is

enabled) or SOSC (if SOSCEN remains set).

Note:

The Primary Oscillator mode has three

different submodes (XT, HS and EC),

which are determined by the POSCMDx

Configuration bits. While an application

can switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

2: Direct clock switches between any

Primary Oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transitional

clock source between the two PLL modes.

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