DVR datasheet(108/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 108

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9.5

Oscillator Modes

The PLL block is shown in Figure 9-2. In this system,

the input from the Primary Oscillator is divided down by

a PLL prescaler to generate a 4 MHz output. This is

used to drive an on-chip, 96 MHz PLL frequency multi-

plier to drive the fixed, divide-by-3 frequency divider

and configurable PLL prescaler/divider to generate a

range of system clock frequencies. The CPDIV<1:0>

bits select the system clock speed. Available clock

options are listed in Table 9-2.

The user must manually configure the PLL divider to

generate the required 4 MHz output using the

PLLMODE<3:0> Configuration bits. This limits the

choices for Primary Oscillator frequency to a total of

eight possibilities, as shown in Table 9-3.

TABLE 9-2:

SYSTEM CLOCK OPTIONS

TABLE 9-3:

VALID PRIMARY OSCILLATOR

CONFIGURATIONS

FIGURE 9-2:

PLL BLOCK

MCU Clock Division

(CPDIV<1:0>)

Microcontroller

Clock Frequency

None (00)32 MHz

2 (01)16 MHz

4 (10)

8MHz

8 (11)

4MHz

Input Oscillator

Frequency

Clock Mode

PLL Mode

(PLLMODE<3:0>)

48 MHz

ECPLL

12 (0111)

32 MHz

HSPLL, ECPLL

8 (0110)

24 MHz

HSPLL, ECPLL

6 (0101)

20 MHz

HSPLL, ECPLL

5 (0100)

16 MHz

HSPLL, ECPLL

4 (0011)

12 MHz

HSPLL, ECPLL

3 (0010)

8 MHz

ECPLL, XTPLL,

FRCPLL

2 (0001)

4 MHz

ECPLL, XTPLL,

FRCPLL

1 (0000)

96 MHz

PLL

4 MHz

PLL Output

for System Clock

CPDIV<1:0>

PLLMODE<3:0>

Input from

POSC

Input from

FRC

(Note 1)

32 MHz

0111

0110

0101

0100

0011

0010

0001

0000

 12

 8

 6

 5

 4

 3

 2

 1

 4

 2

 1

Note 1:

This MUX is controlled by the COSC<2:0> bits when running from the PLL or the NOSC<2:0> bits when

preparing to switch to the PLL.

1100

1101

1110

 3

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