L9396 datasheet(80/109 Pages) STMICROELECTRONICS

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System functional safety implementations

L9396

80/109

DS12539 Rev 6

WD Request Timing

SPI parameters are programmable only before the WD mechanism starts. After the first

seed request, these parameters can be only read.

A WD1_RESET event does not clear programmed parameters; default values are applied

only as a consequence of a WSM_RESET.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

76543210

Addr

T_Req_TimeOut_Delta

T_Valid_Req_End_Delta

T_Valid_Req_Start

CRC

SPI parameter

Size

(bits)

default

Description

T_Valid_Req_Start

0xFF

Start of the timing window inside which requests must be

received. Absolute value.

Time = T_Valid_Req_Start * WD_clk

T_Valid_Req_End_Delta

0x30

End of the timing window inside which requests must be

received. The value specified is an incremental time starting

from T_Valid_Req_Start.

Time = (T_Valid_Req_Start + T_Valid_Req_End_Delta) *

WD_clk

T_Req_TimeOut_Delta

0x00

End of the period for requests acceptance. Once reached, the

WD1_RESET signal will be sent independently of the Error

status (WD_CNT). The value specified is an incremental time

starting from T_Valid_Req_Start and T_Valid_Req_End_Delta.

Time = (T_Valid_Req_Start + T_Valid_Req_End_Delta +

T_Req_TimeOut_Delta) * WD_clk

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