L9396 datasheet(36/109 Pages) STMICROELECTRONICS

36 / 109 page

Power supply

L9396

36/109

DS12539 Rev 6

If the device receives an SPI command to set the POWERHOLD bit within the first keep-

alive period the device remains awake. Similarly, if the device receives an SPI command to

refresh the KEEPALIVE bit within the first keep-alive period the device remains awake.

Once the KEEPALIVE bit is refreshed a new KA_period starts and so forth. To stay on the

keep-alive bit should be refreshed at each KA_period.

Should the KA_period elapse without any of the above 3 conditions, the device exits the

keep-alive mode and enters in power down.

The power down sequence depends on the keep alive choice being done.

In the following figure, the power down sequence related to a H->L transition on the wake-

up input pin without SPI conditioning is shown.

Figure 7. Power down sequence from wake up input

VBATP

13.5V

VCC5_UV

VCC_UV

VPREREG

IGN

VCC5

VCC

RESET

WAKE_FLT_down

KA_period

VCORE

Tflt_VCC5_UVOV/Tflt_VCC_UVOV/Tflt_VCORE_VCOREFDBK_UVOV

VCORE_dly

VDD_UV/VINTA_UV

VDD/VINTA

POR

Tflt_ VDD_OV_UV/Tflt_ VINTA_OV_UV

GADG1901171502PS

Table 16. Power up and power down

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VCC5_dly

VCC5 delay at

power-up

From VPREREG_UV to VCC5

start

-200

µs

VCC_dly

VCC delay at

power-up

From VPREREG_UV to VCC

start

-200

µs

VCORE_dly

VCORE delay at

power-down

From end of KA_period to

VCORE switch off

-200

µs

Ton_RESET

RESET hold time

From regulators in range to

RESET High

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