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L9396 数据表(PDF) 97 Page - STMicroelectronics |
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L9396 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 109 page  0010100 1 4 RS_DATA_RSDR_4 RS_DATA_RSDR_4 R WSS RS DELTA 1st PULSE ch.0 [9:0] RESET SSM RESET WSS RS BASE CURRENT ch.0 [9:0] when bit8 of RS_CTRL is 0 WSS INSTANTANEOUS CURRENT ch.0 [9:0] when bit8 of RS_CTRL is 1 RESET SSM RESET 0010101 1 5 RS_DATA_RSDR_5 RS_DATA_RSDR_5 R WSS RS DELTA 1st PULSE ch.1 [9:0] RESET SSM RESET WSS RS BASE CURRENT ch.1 [9:0] when bit8 of RS_CTRL is 0 WSS INSTANTANEOUS CURRENT ch.0 [9:0] when bit8 of RS_CTRL is 1 RESET SSM RESET 0010110 1 6 RS_DATA_RSDR_6 RS_DATA_RSDR_6 R WSS RS DELTA 1st PULSE ch.2 [9:0] RESET SSM RESET WSS RS BASE CURRENT ch.2 [9:0] when bit8 of RS_CTRL is 0 WSS INSTANTANEOUS CURRENT ch.0 [9:0] when bit8 of RS_CTRL is 1 RESET SSM RESET 0010111 1 7 RS_DATA_RSDR_7 RS_DATA_RSDR_7 R WSS RS DELTA 1st PULSE ch.3 [9:0] RESET SSM RESET WSS RS BASE CURRENT ch.3 [9:0] when bit8 of RS_CTRL is 0 WSS INSTANTANEOUS CURRENT ch.0 [9:0] when bit8 of RS_CTRL is 1 RESET SSM RESET 0011000 1 8 RS_DATA_RSDR_8 RS_DATA_RSDR_8 R - - ---- --- --- ---- - --- WSS RS DELTA 2nd PULSE ch.0 [9:0] RESET SSM RESET 0011001 1 9 RS_DATA_RSDR_9 RS_DATA_RSDR_9 R - - ---- --- --- ---- - --- WSS RS DELTA 2nd PULSE ch.1 [9:0] RESET SSM RESET 0011010 1 10 RS_DATA_RSDR_10 RS_DATA_RSDR_10 R - - ---- --- --- ---- - --- WSS RS DELTA 2nd PULSE ch.2 [9:0] RESET SSM RESET 0011011 1 11 RS_DATA_RSDR_11 RS_DATA_RSDR_11 R - - ---- --- --- ---- - --- WSS RS DELTA 2nd PULSE ch.3 [9:0] RESET SSM RESET 0011100 1 12 RS_DATA_RSDR_12 RS_DATA_RSDR_12 R - - ---- --- --- ---- - - - - - - - - - - - - 0011101 1 13 - RESERVED - - - ---- --- --- ---- - ---- --- --- ---- - ---- --- - 0011110 1 14 - RESERVED - - - ---- --- --- ---- - ---- --- --- ---- - ---- --- - 0011111 1 15 - RESERVED - - - ---- --- --- ---- - ---- --- --- ---- - ---- --- - 0100000 2 0 WD_SEED_ANSW TYPE R/W RESET WSM RESET see wd q&a chapter R/W - - ---- -- - - - - - - - - Table 60. Registers summary (continued) ADDRESS Name Description Type DATA BIN Page [6:4] REG [3:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6543 210 WR WR WR WR WR WR WR W R W R WR WR W R WR WR W R WR WR W R WR WR |
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