L9396 datasheet(83/109 Pages) STMICROELECTRONICS

83 / 109 page

DS12539 Rev 6

83/109

L9396

System functional safety implementations

108

Except the WD_Cnt_Value and WD_RST_Event_Value fields, this register is automatically

cleared once read.

A WD1_RESET event does not clear programmed parameters; default values are applied

only as a consequence of a WSM_RESET.

7.4.2

Second Watchdog (WD2)

When PRN signal input via PRN pin is not in the range of certain frequency, RESET is

asserted. The watchdog logic detects the only rising edge of PRN signal on PRN pin.

When RESET is deasserted (or at WDTDIS deasserting) the WD2 is in IDLE state for at

least TWAIT in order to wait the Microcontroller's logic bist end; after TWAIT the WD2 works

normally.

When PRN signal stops for at least Toff, RESET pin generates low signal for a time equal to

TRL (equal to Ton_RESET). This signal returns to high after TRL and for a time defined as

TRH. If PRN signal is still not a proper one, the RESET signal returns low for TRL and then

back high, repeating the above sequence.

Figure 22. WD2 timing diagram

PRN frequency error is detected if the frequency is higher than 1 kHz and is not detected if

the frequency is lower than 750 Hz. In other words, when the interval between PRN rising

edges is less than 1 ms, watchdog detects PRN over frequency and does not clear WDT

counter. If this condition continues during toff, RESET pin drives low.

WD_RST_ Cnt

Flag set if the WD1_RESET signal has been sent because

error counter reached zero.

0: Ok

1: WD1_RESET because WD_CNT reached the value of zero

WD_RST_Event_Value

Current value of the WD_RST event already sent

SPI parameter

Size

(bits)

default

Description

GADG2501170928PS

RESET

PRN

TRH

TRL

Toff

VSTN

L9396 数据表(PDF) 83 Page - STMicroelectronics

L9396 数据表(HTML) 83 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载