L9396 datasheet(85/109 Pages) STMICROELECTRONICS

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DS12539 Rev 6

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L9396

System functional safety implementations

108

7.5

Fail safe output

L9396 provides the active low FSN output to let the system know the device enters the fail

safe state. It means that the device has left its functional operating range due to:



weak supply conditions or supply over/under voltage detections (see the table below

for the signals monitored),



thermal shutdown (see the table below),



wrong SPI communications or wrong watchdog operation.

During fail-safe conditions, corresponding failure bits are set until the faults disappear and

the flags are read. When the device enters a fail-safe condition, it remains in this state until

both the following criteria are met:



the failure condition disappears,



the microcontroller performs a SPI reading on the failure bit(s).

The FSN output is intended to control functional safety logic through a redundant path

(since the µC is not operational anymore) for up to ASIL-D applications.

The functional safety path is intended to control the applications loads in order to either

maintain the functionality in a degraded mode or deactivate the loads. It is fault tolerant

(programmed from 1 to 8 failures before activation) and has a programmable delay; all this

can be programmed via SPI interface. To exit the fail-safe mode a specific SPI access on

the original failure(s) has to be performed when the application recovers in order to clear the

flags and fail safe fault tolerant counter.

FSN output is enabled (can be driven low) only at the end of power up cycle. This happens

only when undervoltage of regulators (VPREREG, VCC, VCC5, VCORE) is no more present

after power up.

After that FSN stays enabled until power down by wake-up is triggered or undervoltage of

VPREREG is generated.

Here the table of masking bits and fault sources.

Table 55. WDTDIS characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VIL_WDTDIS WDTDIS Logic Input Low Voltage

0.75

VIH_WDTDIS WDTDIS Logic Input High Voltage

1.75

Vhysteresis

WDTDIS Input hysteresis Voltage

0.1

WDTDIS PD WDTDIS pull-down

WDTDIS = 3.3V

100

µA

Table 56. Masking bits and fault sources

FAILSAFE / FAULT

OUTPUT

WD1 and WD2

FAULT MASK

FAILSAFE / FAULT

OUTPUT

THERMAL WARNING

MASK

FAILSAFE / FAULT

OUTPUT

µC VOLTAGE FAULT

MASK

FAILSAFE / FAULT

OUTPUT

BOOST FAULT

MASK

WD Q/A ERR

MASKED

FAILSAFE FAULT

WD PRUN ERR

MASKED

FAILSAFE FAULT

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