数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ES9218PC 数据表(PDF) 33 Page - ESS Technology,Inc

部件名 ES9218PC
功能描述  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  101 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ESS [ESS Technology,Inc]
网页  http://www.esstech.com
标志 ESS - ESS Technology,Inc

ES9218PC 数据表(HTML) 33 Page - ESS Technology,Inc

Back Button ES9218PC Datasheet HTML 29Page - ESS Technology,Inc ES9218PC Datasheet HTML 30Page - ESS Technology,Inc ES9218PC Datasheet HTML 31Page - ESS Technology,Inc ES9218PC Datasheet HTML 32Page - ESS Technology,Inc ES9218PC Datasheet HTML 33Page - ESS Technology,Inc ES9218PC Datasheet HTML 34Page - ESS Technology,Inc ES9218PC Datasheet HTML 35Page - ESS Technology,Inc ES9218PC Datasheet HTML 36Page - ESS Technology,Inc ES9218PC Datasheet HTML 37Page - ESS Technology,Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 33 / 101 page
background image
ES9218P Datasheet
CONFIDENTIAL ADVANCE INFORMATION 1.8
December 6, 2018
33
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
XIN/MCLK Timing
t
MCH
t
MCL
t
MCY
MCLK
t
MCH
t
MCL
t
MCY
MCLK
Figure 8. Clock Timing
Parameter
Symbol
Min
Max
Unit
MCLK pulse width high
TMCH
9.0
90
ns
MCLK pulse width low
TMCL
9.0
90
ns
MCLK cycle time
TMCY
20
200
ns
MCLK duty cycle
45:55
55:45
5������������������ ≤ ������������������������ ≤ 50������������������
Audio Interface Timing
L
t
DCH
t
DCL
t
DCY
DATA_CLK
t
DH
t
DS
DATA[8:1]
Valid
Invalid
Valid
t
DCH
t
DCL
t
DCY
DATA_CLK
t
DH
t
DS
DATA[8:1]
Valid
Invalid
Valid
DATA_CLK
DATA[2:1]
Parameter
Symbol
Min
Max
Unit
DATA_CLK pulse width high
tDCH
9.0
ns
DATA_CLK pulse width low
tDCL
9.0
ns
DATA_CLK cycle time
tDCY
20
ns
DATA_CLK duty cycle
45:55
55:45
DATA set-up time to DATA_CLK rising edge
tDS
4.1
ns
DATA hold time to DATA_CLK rising edge
tDH
2
ns
Figure 9. Audio Interface Timing
Notes:
Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time requirements relative to the
rising edge of DATA_CLK
For DSD Phase mode, the normal data (D0, D1, D2) must satisfy the setup and hold time requirements relative to the rising edge of DATA_CLK.
The complimentary data (D0, D1, etc.) will be ignored.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com