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ES9218PC 数据表(PDF) 52 Page - ESS Technology,Inc |
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ES9218PC 数据表(HTML) 52 Page - ESS Technology,Inc |
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52 / 101 page  ES9218P Datasheet December 6, 2018 CONFIDENTIAL ADVANCE INFORMATION 1.8 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 52 Register 12: ASRC/DPLL Bandwidth (0x0C) Bits [7:4] [3:0] Mnemonic dpll_bw_serial dpll_bw_dsd Default 4’d5 4’d10 Bit Mnemonic Description [7:4] dpll_bw_serial Sets the bandwidth of the DPLL when operating in I2S/DoP mode. • 4’d0: DPLL Off • 4’d1: Lowest Bandwidth • 4’d2: • 4’d3: • 4’d4: • 4’d5: (default) • 4’d6: • 4’d7: • 4’d8: • 4’d9: • 4’d10: • 4’d11: • 4’d12: • 4’d13: • 4’d14: • 4’d15: Highest Bandwidth [3:0] dpll_bw_dsd Sets the bandwidth of the DPLL when operating in DSD mode. • 4’d0: DPLL Off • 4’d1: Lowest Bandwidth • 4’d2: • 4’d3: • 4’d4: • 4’d5: • 4’d6: • 4’d7: • 4’d8: • 4’d9: • 4’d10: (default) • 4’d11: • 4’d12: • 4’d13: • 4’d14: • 4’d15: Highest Bandwidth |
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