ES9218PC datasheet(64/101 Pages) ESS

64 / 101 page

ES9218P Datasheet

December 6, 2018

CONFIDENTIAL ADVANCE INFORMATION 1.8

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Bits

[15:14]

[13:12]

[11:0]

Mnemonic

cp_clk_sel

cp_clk_en

cp_clk_div

Default

2’b00

12’d0

Bit

Mnemonic

Description

[15:14]

cp_clk_sel

Selects which clock will be used as the reference clock for the charge pump (CP) clock.

•

2’b00: use CLK as the CP reference clock (default)

•

2’b01: use 128*fs as the CP reference clock

•

2’b10: use 64*fs as the CP reference clock

•

2’b11: use 1*fs as the CP reference clock

The chargepump clock frequency is not guaranteed to be exactly equal to XI(MCLK). The cp_clk_div

setting is automatically adjusted to undo the effects of clock gearing. The result is that the chargepump

rate remains constant with respect to XI(MCLK) even when CLK changes but only to within the truncation

error of the chargepump clock divider.

See System Clock XI(MCLK) for the relationship between XI(MCLK) and CLK.

[13:12]

cp_clk_en

Sets the state of the charge pump clock.

•

2’b00: tristate output (default, use internal CP oscillator)

•

2’b01: tied to GND

•

2’b10: tied to DVDD

•

2’b11: cp_clk_sel / cp_clk_div

Note: Set cp_clk_div before setting cp_clk_en to 2’b11.

[11:0]

cp_clk_div

Sets the divider ratio for the charge pump clock. f

CLK is the frequency of the clock selected by

cp_clk_sel.

fCP =

fCLK

cp_clk_div ∗ 2

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