ES9218PC datasheet(39/101 Pages) ESS

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ES9218P Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.8

December 6, 2018

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Bits

[7:4]

[3:2]

[1]

[0]

Mnemonic

osc_drv

clk_gear

reserved

soft_reset

Default

4’b0000

2’b00

1’b0

Bit

Mnemonic

Description

[7:4]

osc_drv

Oscillator drive specifies the bias current to the oscillator pad.

•

4’b0000: full bias (default)

•

4’b1000: ¾ bias

•

4’b1100: ½ bias

•

4’b1110: ¼ bias

•

4’b1111: shut down the oscillator

[3:2]

clk_gear

Configures a clock divider network that can reduce the power consumption of the chip by

reducing the clock frequency supplied to both the digital core and analog stages.

•

2’b00: uses CLK = XI(MCLK) (default)

•

2’b01: divides CLK = XI(MCLK) by 2

•

2’b10: divides CLK = XI(MCLK) by 4

•

2’b11: divides CLK = XI(MCLK) by 8

[1]

reserved

[0]

soft_reset

Software configurable hardware reset with the ability to reset the design to its initial power -on

configuration.

•

1’b0: normal operation (default)

•

1’b1: resets the ES9218P to its power-on defaults

Note: This register will always read as “1’b0” as the power-on default for this register is “1’b0”.

A reset can be verified by checking the status of other modified registers.

ES9218PC 数据表(PDF) 39 Page - ESS Technology,Inc

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