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ES9218PC 数据表(PDF) 10 Page - ESS Technology,Inc |
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ES9218PC 数据表(HTML) 10 Page - ESS Technology,Inc |
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10 / 101 page  ES9218P Datasheet December 6, 2018 CONFIDENTIAL ADVANCE INFORMATION 1.8 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 10 40 Pin QFN Pin Descriptions Pin Name Pin Type Reset State Pin Description 1 RT1 I Tri-stated Reserved. Must be connected to DGND for normal operation. 2 XO AO Floating XTAL output 3 XI AI Floating XTAL / MCLK input 4 VCCA Power Power Analog 1.8V/3.3V for OSC and on-chip AVCC_DAC regulator. 5 AGND Ground Ground DAC analog ground (Right Channel) 6 AUX_R AI - Auxiliary analog input (Right Channel) 7 INB_R AI - Amplifier differential inverting input (Right Channel) 8 IN_R AI - Amplifier differential non-inverting input (Right Channel) 9 OUT_R AO - Amplifier output (Right Channel) 10 GSN_R - - Amplifier load ground sense (Right Channel) 11 AGND Ground Ground Analog ground 12 AGND Ground Ground Analog ground 13 PNEG Power Power Amplifier negative supply. Internally supplied. 14 PNEG_VC Power Power AVC negative supply. Internally supplied. 15 C2 - - Amplifier charge pump negative flying capacitor pin. 16 C2_VC - - AVC charge pump negative flying capacitor pin. 17 C1_VC - - AVC charge pump positive flying capacitor pin. 18 C1 - - Amplifier charge pump positive flying capacitor pin. 19 AVCC18 Power Power Analog 1.8V supply for Amplifier, switch, AVC and charge pumps. 20 AVCC33 Power Power Analog 3.3V supply for Amplifier, switch, AVC and charge pumps. 21 GSN_L - - Amplifier load ground sense. Left channel. 22 OUT_L AO - Amplifier output (Left Channel). 23 IN_L AI - Amplifier differential non-inverting input (Left Channel) 24 INB_L AI - Amplifier differential inverting input (Left Channel) 25 AUX_L AI - Auxiliary analog input (Left Channel) 26 AGND Ground Ground DAC analog ground (Left Channel) 27 AVCC_DAC Power Power DAC analog supply. Internally supplied. 28 VREF Power Power Low Noise reference for on-chip AVCC_DAC regulator. 29 AVDD Power Power Digital 1.8V/3.3V supply for I/O and on-chip DVDD regulator. 30 DGND Ground Ground Digital ground. 31 DVDD Power Power Digital core supply. Internally supplied. 32 GPIO2 I/O Tri-stated GPIO 2 *special function in standby* (Aux. Path) 33 GPIO1 I/O Tri-stated GPIO 1 34 DATA_2 I Tri-stated PCM Data Ch1+Ch2 or DSD Data2 (Right Channel) 35 DATA1 I/O Tri-stated Slave Mode: Input for PCM Frame Clock or Input for DSD Data1 (Left Channel) Master Mode: Output for PCM Frame Clock 36 DATA_CLK I/O Tri-stated Slave Mode: Input for PCM Bit Clock or DSD Bit Clock, Master Mode: Output for PCM Bit Clock 37 RESETB I 1'b0 Power down. Active low. 38 SCL I Tri-stated I2C serial clock input. 39 SDA I/O Tri-stated I2C serial data input/output. 40 ADDR I Tri-stated I2C address select. 41 DGND Ground Ground Exposed pad. Digital ground. |
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