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ES9218PC 数据表(PDF) 87 Page - ESS Technology,Inc |
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ES9218PC 数据表(HTML) 87 Page - ESS Technology,Inc |
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87 / 101 page  ES9218P Datasheet CONFIDENTIAL ADVANCE INFORMATION 1.8 December 6, 2018 87 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 Register 65 (Read-Only): GPIO Readback (0x41) Bits [7] [6] [5] [4] [3:2] [1] [0] Mnemonic ocbr_pos ocbl_pos ocbr_neg ocbl_neg clk_gear_rb gpio2 gpio1 Default 1’b0 1’b0 1’b0 1’b0 2’b00 1’b0 1’b0 Bit Mnemonic Description [7] ocbr_pos Indicates instantaneous positive overcurrent condition on the right channel. • 1’b0 No positive overcurrent condition (default) • 1’b1 Positive overcurrent condition at the amplifier output See Overcurrent Protection [6] ocbl_pos Indicates instantaneous positive overcurrent condition on the left channel. • 1’b0 No positive overcurrent condition (default) • 1’b1 Positive overcurrent condition at the amplifier output See Overcurrent Protection [5] ocbr_neg Indicates instantaneous negative overcurrent condition on the right channel. • 1’b0 No negative overcurrent condition (default) • 1’b1 Negative overcurrent condition at the amplifier output See Overcurrent Protection [4] ocbl_neg Indicates instantaneous negative overcurrent condition on the left channel. • 1’b0 No negative overcurrent condition (default) • 1’b1 Negative overcurrent condition at the amplifier output See Overcurrent Protection [3:2] clk_gear_rb Clock gear readback. This register will reflect changes from both manual and automatic clock gearing. • 2’b00: indicates CLK = XI(MCLK) (default) • 2’b01: indicates CLK = XI(MCLK) / 2 • 2’b10: indicates CLK = XI(MCLK) / 4 • 2’b11: indicates CLK = XI(MCLK) / 8 [1] gpio2 Contains the state of the GPIO2 pin. [0] gpio1 Contains the state of the GPIO1 pin. |
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