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TDA4VL...ALZQ1 数据表(PDF) 152 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 152 Page - Texas Instruments |
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152 / 251 page  7.10.5.2 CPSW2G For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within Signal Descriptions and Detailed Description. 7.10.5.2.1 CPSW2G MDIO Interface Timings Table 7-26 represents CPSW2G timing conditions. Table 7-26. CPSW2G MDIO Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input signal slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 7-27, Table 7-28, and Figure 7-35 present timing requirements for MDIO. Table 7-27. CPSW2G MDIO Timing Requirements NO. MIN MAX UNIT MDIO1 tsu(mdioV-mdcH) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(mdcH-mdioV) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 7-28. CPSW2G MDIO Switching Characteristics NO. PARAMETER MIN MAX UNIT MDIO3 tc(mdc) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(mdcH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(mdcL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(mdcL-mdioV) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid –150 150 ns MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 7-35. CPSW2G MDIO Timing Requirements and Switching Characteristics Note x = 0 in MCU domain TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 152 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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