TDA4VL...ALZQ1 datasheet(154/251 Pages) TI

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RMII4

RMII5

RMII[x]_

REF CLK

RMII[x]_RXD[1:0], RMII[x]_CRS_DV,

RMII[x]_RX_ER

Figure 7-37. CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII

Mode

Section 7.10.5.2.2.3, and Figure 7-38 present switching characteristics for CPSW2G RMII Transmit.

7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

see Figure 7-38

NO.

PARAMETER

MIN

MAX UNIT

RMII6

td(ref_clkH-txdV)

Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0] valid

td(ref_clkH-tx_enV)

Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN valid

RMII[x]_TXD[1:0], RMII[x]_TX_EN

RMII6

RMII[x]_REF_CLK

Figure 7-38. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

7.10.5.2.3 CPSW2G RGMII Timings

Section 7.10.5.2.3.1, Section 7.10.5.2.3.2, and Figure 7-40 present timing requirements for receive RGMII

operation.

For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device

TRM.

Table 7-30. CPSW2G RGMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDD(1) = 1.8 V

1.44

V/ns

VDD(1) = 3.3 V

2.64

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

RGMII[x]_RXC,

RGMII[x]_RD[3:0],

RGMII[x]_RX_CTL

RGMII[x]_TXC,

RGMII[x]_TD[3:0],

RGMII[x]_TX_CTL

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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