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TDA4VL...ALZQ1 数据表(PDF) 153 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 153 Page - Texas Instruments |
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153 / 251 page ![]() 7.10.5.2.2 CPSW2G RMII Timings Table 7-29, Section 7.10.5.2.2.1, Section 7.10.5.2.2.2, and Section 7.10.5.2.2.3 present timing conditions, requirements, and switching characteristics for CPSW2G RMII. Table 7-29. CPSW2G RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input signal slew rate VDD(1) = 1.8 V 0.108 0.54 V/ns VDD(1) = 3.3 V 0.4 1.2 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 25 pF (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode see Figure 7-36 NO. MIN MAX UNIT RMII1 tc(ref_clk) Cycle time, RMII[x]_REF_CLK 19.999 20 ns RMII2 tw(ref_clkH) Pulse Duration, RMII[x]_REF_CLK high 7 13 ns RMII3 tw(ref_clkL) Pulse Duration, RMII[x]_REF_CLK low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 A. x = 1 in MCU domain. Figure 7-36. CPSW2G RMII[x]_REFCLK Timing Requirements – RMII Mode 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode NO. MIN MAX UNIT RMII4 tsu(rxdV-ref_clkH) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising edge 4 ns tsu(crs_dvV-ref_clkH) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising edge 4 ns tsu(rx_erV-ref_clkH) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising edge 4 ns RMII5 th(ref_clkH-rxdV) Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-crs_dvV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-rx_erV) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge 2 ns www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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