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TDA4VL...ALZQ1 数据表(PDF) 156 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 156 Page - Texas Instruments |
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156 / 251 page  7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode NO. PARAMETER MODE MIN MAX UNIT RGMII6 tc(txc) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII7 tw(txcH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII8 tw(txcL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode see Figure 7-40 NO. PARAMETER MODE MIN MAX UNIT RGMII9 tosu(tdV-txcV) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns tosu(tx_ctlV-txcV) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII10 toh(tdV-txcV) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns toh(tx_ctlV-txcV) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL _ (B) RGMII9 1st Half-byte TXERR TXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 7-40. CPSW2G Transmit Interface Timing RGMII Mode TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 156 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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