TDA4VL...ALZQ1 datasheet(186/251 Pages) TI

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GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_FCLK

GPMC_WAIT[j]

GNF10

GNF14

GNF15

GNF12

GNF13

DATA

GPMC_AD[15:0]

GPMC_14

GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional

clock edge. GNF12 value must be stored inside AccessTime register bits field.

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.

Figure 7-64. GPMC and NAND Flash — Data Read Cycle

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_WEn

DATA

GNF0

GNF1

GNF4

GNF9

GNF3

GNF6

GPMC_AD[15:0]

GPMC_15

`In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 7-65. GPMC and NAND Flash — Data Write Cycle

For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in

the device TRM.

7.10.5.10.4 GPMC0 IOSET

Table 7-40 present the specific groupings of signals (IOSET) for use with GPMC0.

Table 7-40. GPMC0 IOSET

Signals

IOSET1

IOSET2

BALL NAME

MUX

BALL NAME

MUX

GPMC0_WAIT2

MDIO0_MDC

GPMC0_BE1n

PRG1_PRU0_GPO0

RGMII6_RD1

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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