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TDA4VL...ALZQ1 数据表(PDF) 189 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 189 Page - Texas Instruments |
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189 / 251 page  NO. PARAMETER DESCRIPTION MIN MAX UNIT D12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:D7 valid 0.84 2.17 ns 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT LFD5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.81 0.81 ns LFD6 tc(clk) CLK period, CLK 10 ns LFD7 tw(clk) Pulse width, CLK 4.75 ns LFD8 tw(csIV) Pulse width, CS0 invalid between operations 10 ns LFD9 td(clkH-csL) Delay time, CS0 active to CLK rising -3.51 ns LFD10 td(clkL[LE]-csH) Delay time, last falling CLK edge to CS0 inactive 0.51 ns LFD11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 1.51 3.49 ns LFD12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:D7 valid 1.34 3.66 ns HYPERBUS_TIMING_01 CK, CKn D8/LFD8 D2 RWDS DQ[7:0] D9/LFD9 Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:0 47:40 Dn Dn Dn+1 Dn+1 A B A B D6/LFD6 D7/LFD7 D11/LFD11 D10/LFD10 D12/LFD12 D4 D12/LFD12 CSn Figure 7-66. HyperBus Timing Diagrams – Transmitter Mode HYPERBUS_TIMING_02 RWDS DQ[7:0] Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:0 47:40 Dn Dn Dn+1 Dn+1 A B A B CK, CKn D8/LFD8 D2 D9/LFD9 D6/LFD6 D7/LFD7 D10/LFD10 D4 D12/LFD12 D5/LFD5 D5/LFD5 CSn Figure 7-67. HyperBus Timing Diagrams – Receiver Mode www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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