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TDA4VL...ALZQ1 数据表(PDF) 192 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 192 Page - Texas Instruments |
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192 / 251 page  4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (for example: a short Bus). 5. On a Legacy Bus where I2C Devices need to see Start, the tCAS Min value is further constrained. 6. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3. 7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300ns shorter than the Fm Bus Free Condition time (tBUF). - Open drain with weak pull-up - Open drain with weak pull-up I3C_TIMING_01 SCL SDA D2 D1 D3 D6 Start Stop Repeated Start Stop 0.7xVDD 0.3xVDD 0.7xVDD 0.3xVDD D4 D5 Figure 7-69. I3C Open Drain Timing Table 7-44. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT D1 fSCL SCL Clock Period Controller 80 100000 ns D2 tLOW SCL Clock Low Period Controller 24 ns tDIG_L 32 ns D3 tHIGH_MIXED SCL Clock High Period of Mixed Bus (Mixed Bus Topology Not Supported) Controller 24 ns tDIG_H_MIXED 32 45 ns D4 tHIGH SCL Clock High Period Controller 24 ns tDIG_H 32 ns D5 tSCO Clock in to Data Out for Target Target 12 ns D6 tCR SCL Clock Rise Time Controller 150 × 1 / fSCL 60 ns D7 tCF SCL Clock Fall Time Controller 150 × 1 / fSCL 60 ns D8 tHD_PP SDA Signal Data Hold in Push Pull Mode Controller tCR + 3 and tCF + 3 ns Target 0 ns D9 tSU_PP SDA Signal Data Setup In Push-Pull Mode Controller, Target 3 ns D10 tCASr Clock After Repeated START (Sr) Controller tCAS MIN ns D11 tCBSr Clock Before Repeated START (Sr) Controller tCAS MIN / 2 ns 1. FSCL = 1 / (tDIG_L + tDIG_H) 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH. 3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained to make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling. 4. As both edges are used, the hold time needs to be satisfied for the respective edges; tCF + 3 for falling edge clocks, and tCR + 3 for rising edge clocks. 5. Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 192 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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