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TDA4VL...ALZQ1 数据表(PDF) 191 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 191 Page - Texas Instruments |
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191 / 251 page  • The I2C specification defines a maximum input voltage VIH of (VDD max + 0.5 V), which exceeds the absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals never exceed the limits defined in the Absolute Maximum Ratings section of this data sheet. Refer to the Philips I2C-bus specification version 2.1 for timing details. For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding subsections within Section 6.3 and Detailed Description. 7.10.5.13 I3C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Signal Descriptions, Signal Descriptions and Detailed Description. Table 7-42, Table 7-43, Figure 7-69, Table 7-44, and Figure 7-70 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 7-42. I3C Open Drain Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.2276 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 50 pF Table 7-43. I3C Open Drain Timing Parameters NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT D1 tLOW_OD Low Period of SCL Clock Controller 200 ns tDIG_OD_L tLOW_OD MIN + tFDA_OD MIN ns D2 tHIGH High Period of SCL Clock Controller 41 ns tDIG_H tHIGH + tCF ns D3 tfDA_OD Fall Time of SDA Signal Controller, Target tCF 12 ns D4 tSU_OD SDA Data Setup Time During Open Drain Mode Controller, Target 3 ns D5 tCAS Clock After START (S) Condition Controller, ENTAS0 38.4 1000 ns Controller, ENTAS1 38.4 100000 ns Controller, ENTAS2 38.4 2000000 ns Controller, ENTAS3 38.4 50000000 ns D6 tCBP Clock Before STOP (P) Condition Controller tCAS MIN / 2 ns D7 tMMOVERLAP Current Controller to Secondary Controller Overlap time during handoff Controller tDIG_OD_L min ns D8 tAVAL Bus Available Condition Controller 1000 ns D9 tIDLE Bus Idle Condition Controller 1000000 ns D10 tMMLOCK Time Internal Where New Controller Not Driving SDA Low Controller tAVALmin ns 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin. 2. The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already above VIH. 3. Based on tSPIKE, rise and fall times, and interconnect. www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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