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TDA4VL...ALZQ1 数据表(PDF) 188 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 188 Page - Texas Instruments |
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188 / 251 page  Table 7-40. GPMC0 IOSET (continued) Signals IOSET1 IOSET2 BALL NAME MUX BALL NAME MUX GPMC0_A15 RGMII6_TD3 8 RGMII6_TD3 8 GPMC0_A16 RGMII6_TD2 8 RGMII6_TD2 8 GPMC0_A17 RGMII6_TD1 8 RGMII6_TD1 8 GPMC0_A18 RGMII6_TD0 8 RGMII6_TD0 8 GPMC0_A19 RGMII6_TXC 8 RGMII6_TXC 8 GPMC0_A20 RGMII6_RXC 8 RGMII6_RXC 8 GPMC0_A21 RGMII6_RD3 8 RGMII6_RD3 8 GPMC0_A22 RGMII6_RD2 8 RGMII6_RD2 8 GPMC0_A23 PRG0_PRU1_GPO2 8 PRG0_PRU1_GPO2 8 GPMC0_A24 PRG0_PRU1_GPO4 8 PRG0_PRU1_GPO4 8 GPMC0_A25 PRG0_PRU1_GPO6 8 PRG0_PRU1_GPO6 8 GPMC0_A26 PRG0_PRU1_GPO11 8 PRG0_PRU1_GPO11 8 GPMC0_A27 PRG0_MDIO0_MDIO 8 PRG0_MDIO0_MDIO 8 GPMC0_WAIT3 MDIO0_MDIO 8 MDIO0_MDIO 8 7.10.5.11 HyperBus For more details about features and additional description information on the device HyperBus, see the corresponding sections within Signal Descriptions and Detailed Description. Section 7.10.5.11, Section 7.10.5.11.2, and Section 7.10.5.11.3 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 7-66, Figure 7-67, and Figure 7-68). Table 7-41 represents HyperBus timing conditions. Table 7-41. HyperBus Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 7.10.5.11.1 Timing Requirements for HyperBus NO. PARAMETER DESCRIPTION MIN MAX UNIT D1 tw(RESETn) Pulse width, RESETn 200 ns D2 tw(csL) Pulse width, Chip Select 1000 ns D3 td(RESETnH-csL) Delay time, RESETn inactive to CSn active 200.34 ns D4 td(csL-RWDSL) Delay time, CSn active to RWDS falling 115 ns 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT D5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.46 0.46 ns D6 tc(clk/clkn) CLK period, CLK/CLKn 6 ns D7 tw(clk/clkn) Pulse width, CLK/CLKn 2.7 ns D8 tw(csIV) Pulse width, CS0 invalid between operations 6 ns D9 td(clkH-csL) Delay time, CS0 active to CLK rising/ CLKn falling -3.34 ns D10 td(clkL[LE]-csH) Delay time, last falling CLK/ rising CLKn edge to CS0 inactive 0.41 ns D11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 1.01 2.08 ns TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 188 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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