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STM32F103CBU6TR 数据表(PDF) 77 Page - STMicroelectronics |
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STM32F103CBU6TR 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 116 page ![]() DS5319 Rev 18 77/116 STM32F103x8, STM32F103xB Electrical characteristics 115 Figure 38. Typical connection diagram using the ADC 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 35 for the value of the pad capacitance). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 35 for the values of Ilkg. 4. Refer to Figure 14. General PCB design guidelines Power supply decoupling must be performed as shown in Figure 39 or Figure 40, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality), and placed as close as possible to the chip. Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. MSv67871V3 Sample-and-hold ADC converter Converter Cparasitic (2) Ilkg (3) CADC VDDA (4) RAIN (1) VAIN RADC VREF+ (4) VSSA I/O analog switch Sampling switch with multiplexing VSS VSS VREF+ (see note 1) STM32F103xx VDDA VSSA /VREF– (see note 1) 1 μF // 10 nF 1 μF // 10 nF ai14388b |
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