STM32U545NET3QTR datasheet(52/283 Pages) STMICROELECTRONICS

52 / 283 page

Functional overview

STM32U545xx

52/283

DS14216 Rev 1

•

Four concurrent DMA channels:

–

Intra-channel DMA transfers chaining via programmable linked-list into memory,

supporting two execution modes: run-to-completion and link step mode

–

Intra-channel and inter-channel DMA transfers chaining via programmable DMA

input triggers connection to DMA task completion events

•

Per linked-list item within a channel:

–

Separately programmed source and destination transfers

–

Programmable data handling between source and destination: byte-based

padding or truncation, sign extension and left/right realignment

–

Programmable number of data bytes to be transferred from the source, defining

the block level

–

Linear source and destination addressing: either fixed or contiguously

incremented addressing, programmed at a block level, between successive

single transfers

–

Programmable DMA request and trigger selection

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Programmable DMA half-transfer and transfer complete events generation

–

Pointer to the next linked-list item and its data structure in memory, with automatic

update of the DMA linked-list control registers

•

Debug:

–

Channel suspend and resume support

–

Channel status reporting and event flags

•

TrustZone support

–

Support for secure and nonsecure DMA transfers, independently at a first channel

level, and independently at a source/destination and link sub-levels

–

Secure and nonsecure interrupts reporting, resulting from any of the respectively

secure and nonsecure channels

–

TrustZone-aware AHB slave port, protecting any DMA secure resource (register,

•

Privileged/unprivileged support:

–

Support for privileged and unprivileged DMA transfers, independently at

channel level

–

Privileged-aware AHB slave port

Table 13. LPDMA1 channels implementation and usage

Channel

Hardware parameters

Features

dma_fifo_

size[x]

dma_

addressing[x]

x = 0 to 3

Channel x (x = 0 to 3) is implemented with:

– no FIFO. Only a single source transfer cell is internally registered.

– fixed/contiguously incremented addressing

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