STM32U545NET3QTR datasheet(69/283 Pages) STMICROELECTRONICS

69 / 283 page

DS14216 Rev 1

69/283

STM32U545xx

Functional overview

3.35

Secure advanced encryption standard hardware accelerator

(SAES)

and encryption standard hardware accelerator (AES)

The devices embed two AES accelerators: SAES and AES. The SAES with hardware

unique key embeds protection against differential power analysis (DPA) and related side

channel attacks. The SAES can share its current key register information with the faster

AES using a dedicated hardware bus.

The SAES and the AES can be used to both encrypt and decrypt data using the AES

algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)

as defined by Federal Information Processing Standards Publication (FIPS PUB 197,

Nov 2001).

Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB and CBC

chaining is supported by both SAES and AES, while CTR, CCM, GCM and GMAC chaining

is only supported by the AES.

SAES and AES support DMA single transfers for incoming and outgoing data (two DMA

channels required).

The SAES supports the selection of all the following key sources, while the AES support

only the first:

•

256-bit software key, written by the application in the key registers (write only)

•

256-bit derived hardware unique key (DHUK), computed inside the SAES engine from

a non-volatile OTP based root hardware unique key (RHUK)

•

256-bit boot hardware key (BHK), stored in tamper-resistant secure backup registers,

written by a secure code during boot. Once written, this key cannot be read or write by

any application until the next product reset.

•

XOR of DHUK (provisioned chip secret) and BHK (software secret)

DHUK, BHK and their XOR are not visible by any software (even secure).

Note:

128-bit key size can also be selected.

BHK key is cleared in case of tamper or RDP regression.

When the SAES is secure (respectively nonsecure), DHUK secure (respectively nonsecure)

is used.

The SAES peripheral is connected by hardware to the true random number generator RNG

(for side-channel resistance).

The SAES and AES peripherals support:

•

Compliant implementation of standard NIST Special Publication 197, Advanced

Encryption Standard (AES) and Special Publication 800-38A, Recommendation for

Block Cipher Modes of Operation

•

128-bit data block processing

•

Support for cipher keys length of 128-bit and 256-bit

•

Encryption and decryption with multiple chaining modes:

–

Electronic codebook (ECB) mode

–

Cipher block chaining (CBC) mode

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