STM32U545NET3QTR datasheet(56/283 Pages) STMICROELECTRONICS

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Functional overview

STM32U545xx

56/283

DS14216 Rev 1

The OCTOSPI registers can be configured as secure through the TZSC controller.

3.24

Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input

clock. The phase of the output clock must be programmed by the user application. The

output clock is then used to clock the data received by another peripheral such as

a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may

require the application to re-configure and recenter the output clock phase with the received

data.

The delay block main features are:

•

Input clock frequency ranging from 25 to 160 MHz

•

Up to 12 oversampling phases

3.25

Analog-to-digital converter (ADC1 and ADC4)

The devices embed two successive approximation analog-to-digital converters.

Table 15. ADC features

ADC modes/features(1)

1. X = supported.

ADC1

ADC4

Resolution

14 bits

12 bits

Maximum sampling speed for 14-bit resolution

2.5 Msps

Hardware offset calibration

Hardware linearity calibration

Single-ended inputs

Differential inputs

Injected channel conversion

Oversampling

up to x1024

up to x256

Data register

32 bits

16 bits

DMA support

Parallel data output to MDF

Autonomous mode

Offset compensation

Gain compensation

Number of analog watchdogs

Wake-up from Stop mode

X(2)

2. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

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