STM32U545NET3QTR datasheet(20/283 Pages) STMICROELECTRONICS

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Functional overview

STM32U545xx

20/283

DS14216 Rev 1

Functional overview

3.1

Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for

microcontrollers and deeply embedded applications, especially those requiring efficient

security.

The Cortex-M33 processor delivers a high computational performance with low-power

consumption and an advanced response to interrupts. It features:

•

Arm TrustZone technology, using the Armv8-M main extension supporting secure and

nonsecure states

•

MPUs (memory protection units), supporting up to 16 regions for secure and

nonsecure applications

•

Configurable SAU (secure attribute unit) supporting up to eight memory regions as

secure or nonsecure

•

Floating-point arithmetic functionality with support for single precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing

and a complex algorithm execution.

The Cortex-M33 processor supports the following bus interfaces:

•

System AHB bus:

The S-AHB (system AHB) bus interface is used for any instruction fetch and data

access to the memory-mapped SRAM, peripheral, external RAM and external device,

or Vendor_SYS regions of the Armv8-M memory map.

•

Code AHB bus:

The C-AHB (code AHB) bus interface is used for any instruction fetch and data access

to the code region of the Armv8-M memory map.

Figure 1 shows the general block diagram of the STM32U545xx devices.

3.2

ART Accelerator (ICACHE and DCACHE)

3.2.1

Instruction cache (ICACHE)

The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve

performance when fetching instruction (or data) from both internal and external memories.

ICACHE offers the following features:

•

Multi-bus interface:

–

Slave port receiving the memory requests from the Cortex-M33 C-AHB code

execution port

–

Master1 port performing refill requests to internal memories (flash memory and

SRAMs)

–

Master2 port performing refill requests to external memories (external flash

memory and RAMs through Octo-SPI)

–

Second slave port dedicated to ICACHE registers access

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