STM32U545NET3QTR datasheet(77/283 Pages) STMICROELECTRONICS

77 / 283 page

DS14216 Rev 1

77/283

STM32U545xx

Functional overview

•

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

•

Two programmable alarms

•

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock

•

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision

•

Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy

•

Timestamp feature that can be used to save the calendar content. This function can be

triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode

•

17-bit auto-reload wake-up timer (WUT) for periodic events with programmable

resolution and period

•

TrustZone support:

–

RTC fully securable

–

Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure

configuration

–

Alarm A, alarm B, wake-up timer and timestamp individual privileged protection

The RTC is supplied through a switch that takes power either from the VDD supply when

present or from the VBAT pin.

The RTC clock sources can be one of the following:

•

32.768 kHz external crystal (LSE)

•

external resonator or oscillator (LSE)

•

internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

•

high-speed external clock (HSE), divided by a prescaler in the RCC.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in

all low-power modes except Shutdown mode.

All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake-up

the device from the low-power modes.

3.40.2

Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32

32-bit backup registers are retained in all low-power modes and also in VBAT mode. The

backup registers, as well as other secrets in the device, are protected by this anti-tamper

detection circuit with eight tamper pins and eleven internal tampers. The external tamper

pins can be configured for edge detection, or level detection with or without filtering, or

active tamper that increases the security level by auto checking that the tamper pins are not

externally opened or shorted.

TAMP main features:

•

A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches

and cryptographic peripherals.

•

32 32-bit backup registers:

–

The backup registers (TAMP_BKPxR) are implemented in the backup domain that

remains powered-on by VBAT when the VDD power is switched off.

STM32U545NET3QTR 数据表(PDF) 77 Page - STMicroelectronics

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