STM32U545NET3QTR datasheet(117/283 Pages) STMICROELECTRONICS

117 / 283 page

62 A3 96

PB9

I/O

FT_fh

IR_OUT, TIM4_CH4, SAI1_D2,

I2C1_SDA, SPI2_NSS,

SDMMC1_CDIR,

FDCAN1_TX(boot),

DCMI_D7/PSSI_D7,

SDMMC1_D5, SAI1_FS_A,

TIM17_CH1, EVENTOUT

PE0

I/O

FT_h

TIM4_ETR, DCMI_D2/PSSI_D2,

LPGPIO1_P13, TIM16_CH1,

EVENTOUT

PE1

I/O

FT_h

DCMI_D3/PSSI_D3, TIM17_CH1,

EVENTOUT

A11 62A2A14

VDD11

B10 63 B7 B13

99 D10

63 D6 99

VSS

A13 64A8A16 100

64E4 100

VDD

1. Function availability depends on the chosen device.

2. PC13, PC14, and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs

in output mode is limited:

- The speed must not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (for example to drive a LED).

3. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the

system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.

4. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

5. Power supply is VDDIO2.

Table 27. STM32U545xx pin/ball definitions(1) (continued)

Pin number

Pin name

(function

after reset)

Alternate functions

Additional

functions

STM32U545NET3QTR 数据表(PDF) 117 Page - STMicroelectronics

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