BLUENRG-332VC datasheet(6/67 Pages) STMICROELECTRONICS

部件名	BLUENRG-332VC

功能描述	Programmable Bluetooth® Low Energy wireless SoC

PDF	67 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

6 / 67 page

Functional overview

2.1

System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

•

Three masters:

–

CPU (Cortex-M0+) core S-bus

–

DMA1

–

Radio system

•

Seven slaves:

–

Internal flash memory on CPU (Cortex-M0+) S bus

–

Internal SRAM0 (12 Kbytes)

–

Internal SRAM1 (12 Kbytes)

–

APB0 peripherals (through an AHB to APB bridge)

–

APB1 peripherals (through an AHB to APB bridge)

–

AHB0 peripherals

–

AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even

when several high-speed peripherals work simultaneously.

Figure 2. Bus matrix

CPU ARM

Cortex-M0+

SRAM1

Flash

Controller

Radio

system

APB1

DMA 1

APB0

AHB0

APB2

SRAM0

Bus matrix

BlueNRG-LPS

Functional overview

DS13819 - Rev 4

page 6/67

BLUENRG-332VC 数据表(PDF) 6 Page - STMicroelectronics

BLUENRG-332VC 数据表(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载