BLUENRG-332VC datasheet(7/67 Pages) STMICROELECTRONICS

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2.2

Arm Cortex-M0+ core with MPU

The BlueNRG-LPS contains an Arm Cortex-M0+ microcontroller core. The Arm® Cortex®-M0+ was developed to

provide a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power

consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M0+ can run from 1 MHz up to 64 MHz.

The Arm Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a

2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small

but powerful instruction set and extensively optimized design, providing high-end processing hardware including a

single-cycle multiplier.

The interrupts are handled by the Arm Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls

specific Arm Cortex-M0+ interrupts as well as the BlueNRG-LPS peripheral interrupts. With its embedded ARM

core, the BlueNRG-LPS family is compatible with all ARM tools and software.

2.3

Memories

2.3.1

Embedded flash memory

The flash controller implements the erase and program flash memory operation. The flash controller also

implements the read and write protection.

The flash memory features are:

•

Memory organization:

–

1 bank of 192 Kbytes

–

Page size: 2 Kbytes

–

Page number 96

•

32-bit wide data read/write

•

Page erase and mass erase

The flash controller features are:

•

flash memory read operations: single read or mass read

•

flash memory write operations: single data write or 4x32-bits burst write or mass write

•

flash memory erase operations: page erase or mass erase

•

page write protect mechanism: 4 variable-size memory segments

2.3.2

Embedded SRAM

The BlueNRG-LPS has a total of 24 Kbytes of embedded SRAM, split into two banks as shown in the following

table:

Table 1. SRAM overview

SRAM bank

Size

Address

Retained in DEEPSTOP

SRAM0

12 Kbytes

0x2000 0000

Always

SRAM1

12 Kbytes

0x2000 3000

Programmable by the user

2.3.3

Embedded ROM

The BlueNRG-LPS has a total of 7 Kbytes of embedded ROM. This area is ST reserved and contains:

•

The UART bootloader from which the CPU boots after each reset (first 6 Kbytes of ROM memory)

•

Some ST reserved values including the ADC trimming values (the last 1 Kbyte of ROM memory)

2.3.4

Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbyte dedicated for user data. The OTP data cannot be

erased.

The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a

system reset. This operation freezes the OTP memory from further unwanted write operations.

BlueNRG-LPS

Arm Cortex-M0+ core with MPU

DS13819 - Rev 4

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