BLUENRG-332VC datasheet(17/67 Pages) STMICROELECTRONICS

17 / 67 page

•

SPI: when using the I2S mode, the baud rate is managed through the always 16 MHz or always 32 MHz

clock or system clock (CLK_SYS) to reach higher baud rates. When running in other modes than the I2S,

the baud rate is managed by the system clock. This implies its baud rate is impacted by dynamic system

clock frequency changes.

•

RNG: in parallel with the system clock, the RNG uses an always 16 MHz clock to generate at a constant

frequency the random number whatever the system clock frequency

•

Flash controller: in parallel with the system clock, the flash controller uses an always 16 MHz clock to

generate specific delays required by the flash memory during programming and erase operations for

example

•

PKA: in parallel with the system clock, the PKA uses the system clock frequency

•

Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a

potential divider (1 or 2 or 4). In parallel, the radio uses an always 16 MHz and an always 32 MHz for

modulator, demodulator and to have a fixed reference clock to manage specific delays

•

ADC: in parallel with the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz

2.10

Boot mode

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This

modification is performed by programming the REMAP bit in the flash controller.

The following memory can be remapped:

•

main flash memory

•

SRAM0 memory

2.11

Embedded UART bootloader

The BlueNRG-LPS has a pre-programmed bootloader supporting UART protocol with automatic baud rate

detection. The main features of the embedded bootloader are:

•

auto baud rate detection up to 1 Mbps

•

flash mass erase, section erase

•

flash programming

•

flash readout protection enable/disable

The pre-programmed bootloader is an application, which is stored in the BlueNRG-LPS internal ROM at

manufacturing time by STMicroelectronics. This application allows upgrading of the device flash memory with

a user application using a serial communication channel (UART).

Bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application residing in

flash memory is launched.

Note:

Bootloader protocol is described in a separate application note (the UART bootloader protocol, AN5471)

2.12

General purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid

spurious writing to the I/Os registers.

2.13

Direct memory access (DMA)

The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as

memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources

are free for other operations.

The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.

DMA main features are:

•

Eight independently configurable channels (requests)

•

Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also

supported on each channel. This configuration is done by software

BlueNRG-LPS

Boot mode

DS13819 - Rev 4

page 17/67

BLUENRG-332VC 数据表(PDF) 17 Page - STMicroelectronics

BLUENRG-332VC 数据表(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载