BLUENRG-332VC datasheet(14/67 Pages) STMICROELECTRONICS

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2.7.3

SHUTDOWN mode

The SHUTDOWN mode is the least power consuming mode.

The conditions to enter SHUTDOWN mode are the same conditions needed to enter DEEPSTOP mode except

that the LPMS bit of the power controller unit is 1.

In SHUTDOWN mode, the BlueNRG-LPS is in ultra-low power consumption: all voltage regulators, clocks and the

RF interface are not powered. The BlueNRG-LPS can enter shutdown mode by internal software sequence. The

only way to exit shutdown mode is by asserting and deasserting the RSTN pin.

In SHUTDOWN mode:

•

The system is powered down as both the regulators are OFF

•

The VDDIO power domain is ON

•

All the clocks are OFF, LSI and LSE are OFF

•

The I/Os pull-up and pull-down can be controlled during SHUTDOWN mode, depending on the software

configuration

•

The only wake-up source is a low pulse on the RSTN pin

The exit from SHUTDOWN is similar to a POR startup. The PDR feature can be enabled or disabled during

SHUTDOWN.

2.8

Reset management

The BlueNRG-LPS offers two different resets:

•

The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and

corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset

impacts all resources of the BlueNRG-LPS. The exit from SHUTDOWN mode is equivalent to a POR and

thus generates a PORESETn. The PORESETn signal is active when the power supply of the device is

below a threshold value or when the regulator does not provide the target voltage.

•

The PADRESETn (system reset): this reset is built through several sources:

–

PORESETn

–

Reset due to the watchdog

The BlueNRG-LPS device embeds a watchdog timer, which may be used to recover from software

crashes

–

Reset due to CPU Lockup

The Cortex-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an

unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex-M0+

–

Software system reset

The system reset request is generated by the debug circuitry of the Cortex-M0+. The debugger sets

the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system

reset request through the AIRCR can also be done by the embedded software (into the hardfault

handler for instance)

–

Reset from the RSTN external pin

The RSTN pin toggles to inform that a reset has occurred

This PADRESETn resets all resources of the BlueNRG-LPS, except:

–

Debug features

–

Flash controller key management

–

RTC timer

–

Power controller unit

–

Part of the RCC registers

The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case

of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.

BlueNRG-LPS

Reset management

DS13819 - Rev 4

page 14/67

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