BLUENRG-332VC datasheet(21/67 Pages) STMICROELECTRONICS

21 / 67 page

The LPUART has a clock domain independent from the CPU clock, and can wake up the system from

DEEPSTOP mode using baud rates up to 9600 baud. The wake-up events from Stop mode are programmable

and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even

in DEEPSTOP mode, the LPUART can wait for an incoming frame while having an extremely low energy

consumption. Higher speed clock can be used to reach higher baud rates in RUN mode.

The LPUART interfaces can be served by the DMA controller.

2.22

Serial peripheral interface (SPI)

The BlueNRG-LPS has one SPI interface (SPI3) allowing communication up to 32 Mbit/s in both master and slave

modes. The SPI peripheral supports:

•

Master or slave operation

•

Multimaster support

•

Full-duplex synchronous transfers on three lines

•

Half-duplex synchronous transfer on two lines (with bidirectional data line)

•

Simplex synchronous transfers on two lines (with unidirectional data line)

•

Serial communication with external devices

•

NSS management by hardware or software for both master and slave: dynamic change of master/slave

operations

•

SPI Motorola support

•

SPI TI mode support

•

Hardware CRC feature for reliable communication

All SPI interfaces can be served by the DMA controller.

2.23

Inter-IC sound (I2S)

The BlueNRG-LPS SPI interface SPI3 supports the I2S protocol. The I2S interface can operate in slave or master

mode with half-duplex communication. It can address four different audio standards:

•

Philips I2S standard

•

MSB-justified standards (left-justified)

•

LSB-justified standards (right-justified)

•

PCM standard.

The I2S interfaces DMA capability for transmission and reception.

2.24

Serial wire debug port

The BlueNRG-LPS embeds an ARM SWD interface that allows interactive debugging and programming of the

device. The interface is composed of only two pins: SWDIO and SWCLK. The enhanced debugging features for

developers allow up to 4 breakpoints and up to 2 watchpoints.

2.25

TX and RX event alert

The BlueNRG-LPS is provided with the TX_SEQUENCE and RX_SEQUENCE signals which alert, respectively,

transmission and reception activities.

A signal can be enabled for TX and RX on two pins, through alternate functions:

•

TX_SEQUENCE is available on PA10 (AF2) or PB14 (AF1).

•

RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2).

The signal is high when radio is in TX (or RX), low otherwise.

The signals can be used to control external antenna switching and support coexistence with other wireless

technologies.

BlueNRG-LPS

Serial peripheral interface (SPI)

DS13819 - Rev 4

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