INGT165B / INGR165B
10/2003 - rev. 2.0
15 of 21
INGT165B TRANSMITTER PIN DEFINITION
Pin Name
Pin #
Direction
Active
Description
PDATA[0]
A5
INCMOS
High
Parallel data input, Bit 0
PDATA[1]
B5
INCMOS
High
Parallel data input, Bit 1
PDATA[2]
A4
INCMOS
High
Parallel data input, Bit 2
PDATA[3]
B4
INCMOS
High
Parallel data input, Bit 3
PDATA[4]
A3
INCMOS
High
Parallel data input, Bit 4
PDATA[5]
B3
INCMOS
High
Parallel data input, Bit 5
PDATA[6]
A2
INCMOS
High
Parallel data input, Bit 6
PDATA[7]
B2
INCMOS
High
Parallel data input, Bit 7
PDATA[8]
B1
INCMOS
High
Parallel data input, Bit 8
PDATA[9]
C1
INCMOS
High
Parallel data input, Bit 9
PDATA[10]
D2
INCMOS
High
Parallel data input, Bit 10
PDATA[11]
E3
INCMOS
High
Parallel data input, Bit 11
PDATA[12]
D1
INCMOS
High
Parallel data input, Bit 12
PDATA[13]
E2
INCMOS
High
Parallel data input, Bit 13
PDATA[14]
E1
INCMOS
High
Parallel data input, Bit 14
PDATA[15]
F2
INCMOS
High
Parallel data input, Bit 15
PDATA[16]
G3
INCMOS
High
Parallel data input, Bit 16
PDATA[17]
G1
INCMOS
High
Parallel data input, Bit 17
PDATA[18]
H3
INCMOS
High
Parallel data input, Bit 18
PDATA[19]
H2
INCMOS
High
Parallel data input, Bit 19
PDATA[20]
J1
INCMOS
High
Parallel data input, Bit 20
PDATA[21]
J2
INCMOS
High
Parallel data input, Bit 21
PDATA[22]
L1
INCMOS
High
Parallel data input, Bit 22
PDATA[23]
K3
INCMOS
High
Parallel data input, Bit 23
PDATA[24]
K2
INCMOS
High
Parallel data input, Bit 24
PDATA[25]
M1
INCMOS
High
Parallel data input, Bit 25
PDATA[26]
L3
INCMOS
High
Parallel data input, Bit 26
PDATA[27]
M2
INCMOS
High
Parallel data input, Bit 27
PDATA[28]
N2
INCMOS
High
Parallel data input, Bit 28
PDATA[29]
P2
INCMOS
High
Parallel data input, Bit 29
PDATA[30]
N3
INCMOS
High
Parallel data input, Bit 30
PDATA[31]
P3
INCMOS
High
Parallel data input, Bit 31
PDATA[32]
N4
INCMOS
High
Parallel data input, Bit 32
PDATA[33]
P4
INCMOS
High
Parallel data input, Bit 33
PDATA[34]
N5
INCMOS
High
Parallel data input, Bit 34
PDATA[35]
P5
INCMOS
High
Parallel data input, Bit 35
PARITY
C6
INCMOS
High
Parity input
RDCLK
B6
OUTCMOS High
Read clock. PDATA[35..0] is registered at rising edge
VALID
N6
INCMOS
High
Data valid signal
RESET#
A6
INCMOS
Low
Asynchronous reset signal
FLAGI
M6
INCMOS
High
Set FLAG
PARGEN
N1
INCMOS
High
Generate parity internally
SYNGEN
D3
INCMOS
High
Reserved for future functionality, has to be set to ‘0’
PERR#
P6
OUTCMOS Low
Parity error
LOCK
C7
OUTCMOS High
PLL lock indication
OSC
A10
INCMOS
Reference clock input, 66MHz
SDATA
K12
OUTCML
Differential serial high-speed CML output
SDATA#
J14
OUTCML
Differential serial high-speed CML output
EXTRC1
H13
External loop filter pin1
EXTRC2
H12
External loop filter pin2
GND--D
C2, C5, F3, G2, J3, L2, M5
GND
Digital chip (CMOS) power supply GND
GND--ID
A7, P7
GND
Chip interface digital chip power supply GND
GND--IA
G6, G7, G8, G9, J6, J7, J8, J9,
K7, K8
GND
Chip interface analog chip power supply GND
GND--A0
C9, C11, D10, D14, K14, L10
GND
Analog chip (Bipolar) power supply GND
GND--A1
G12, G13
GND
Analog chip (Bipolar) PLL circuit power supply ground
VCC--D
C4, F1, H1, K1, M4
VCC
Digital chip (CMOS) power supply VCC
VCC--ID
B7, N7
VCC
Chip interface digital chip power supply VCC
VCC--IA
E7, E8, E9, E10, F6, F7, F8,
F9, F10, F11, H6, H7, H8, H9
VCC
Chip interface analog chip power supply VCC
VCC--A0
A11, D9, L9, L11, M9
VCC
Analog chip (Bipolar) power supply VCC
VCC--A1
H14, J11
VCC
Analog chip (Bipolar) PLL circuit power supply VCC
Table 15: GigaSTaR® INGT165B Pin Definition
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