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INGT165B / INGR165B
10/2003 - rev. 2.0
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2.2.4 Single Word Transfers
Single Word Transfers are used to support lower data rates than the maximum parallel data rate of
148.5 MByte/s. VALID has to be de-asserted after the parallel read cycle signaled by one RDCLK pulse.
Only one data word is transmitted.
In the timing diagram PARGEN is de-asserted and the application delivers the PARITY bit synchronously
to the data word.
Figure 5: INGT165B Single Word Transfer Timing Diagram
Parameter
Description
Min.
Typ.
Max.
Unit
t6
Setup time PDATA and PARITY to RDCLK rising edge
9
6
ns
t7
VALID active to rising RDCLK edge
9
12
14
ns
t7-1
VALID high state
5
4
ns
t7-2
LOCK# / RESET# high state before TX operational *
50
µs
t8
PDATA and PARITY hold time
9
6
ns
t9
RDCLK high state (without assertion of FLAGI)
14
15
16
ns
t10
Rising RDCLK edge to sampling window for VALID state
(VALID=0: continue single word mode,
VALID=1: enter BURST mode)
18
20
22
ns
Note : For timings with assertion of FLAGI, please see section 3.2.5
* A dislock pulse generates an internal transmitter reset. Therefore both signals have to be at least
50us at high state before transmitter is operational.
Table 2: INGT165B Single Word Transfer Timing Parameters (Under recommended operating conditions)
VALID
RDCLK
PDATA [0..35]
PARITY
DW1
t7
t8
t9
t10
t7-1
LOCK#
PARITY1
t6
t7-2
RESET#
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