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ADN2817 数据表(PDF) 4 Page - Analog Devices

部件名 ADN2817
功能描述  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
PDF  35 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN2817 数据表(HTML) 4 Page - Analog Devices

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ADN2817/ADN2818
Preliminary Technical Data
Rev. PrA | Page 4 of 35
Parameter
Conditions
Min
Typ
Max
Unit
DATA RATE READBACK ACCURACY
Coarse Readback
(See Table 14)
10
%
Fine Readback
In addition to REFCLK accuracy
Data rate < 20 Mb/s
200
ppm
Data rate > 20 Mb/s
100
ppm
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT
200
TBD
mA
OPERATING TEMPERATURE RANGE
–40
+85
°C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
OC-48
TBD
kHz
OC-12
TBD
kHz
OC-3
TBD
kHz
Jitter Peaking
OC-48
0
TBD
dB
OC-12
0
TBD
dB
OC-3
0
TBD
dB
Jitter Generation
OC-48, 12 kHz to 20 MHz
0.001
TBD
UI rms
0.02
TBD
UI p-p
OC-12, 12 kHz to 5 MHz
0.001
TBD
UI rms
0.01
TBD
UI p-p
OC-3, 12 kHz to 1.3 MHz
0.001
TBD
UI rms
0.01
TBD
UI p-p
Jitter Tolerance
OC-48, 223 − 1 PRBS
600 Hz
TBD
UI p-p
6 kHz
TBD
UI p-p
100 kHz
TBD
UI p-p
1 MHz
TBD
UI p-p
20 MHz
TBD
UI p-p
OC-12, 223 − 1 PRBS
30 Hz1
TBD
UI p-p
300 Hz1
TBD
UI p-p
25 kHz
TBD
UI p-p
250 kHz1
TBD
UI p-p
OC-3, 223 − 1 PRBS
30 Hz1
TBD
UI p-p
300 Hz1
TBD
UI p-p
6500 Hz
TBD
UI p-p
65 kHz
TBD
UI p-p
Power Supply Rejection
See Figure XX.
TBD
dB
1 Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.



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