ADN2817 datasheet(21/35 Pages) AD

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Preliminary Technical Data

ADN2817/ADN2818

Rev.Pr A | Page 21 of 35

HYSTERESIS

LOS OUTPUT

INPUT LEVEL

LOS THRESHOLD

Figure 20. ADN2817 LOS Detector Hysteresis

The LOS detector and the SLICE level adjust can be used

simultaneously on the ADN2817/ADN2818. This means that

any offset added to the input signal by the SLICE adjust pins

does not affect the LOS detector’s measurement of the absolute

input level.

SQUELCH MODE

Two squelch modes are available with the ADN2817/ADN2818.

Squelch DATAOUT AND CLKOUT mode is selected when

CTRLC[1] = 0 (default mode). In this mode, when the squelch

input, Pin 27, is driven to a TTL high state, both the clock and

data outputs are set to the zero state to suppress downstream

processing. If the squelch function is not required, Pin 27

should be tied to VEE.

Squelch DATAOUT OR CLKOUT mode is selected when

CTRLC[1] is 1. In this mode, when the squelch input is driven

to a high state, the DATAOUT pins are squelched. When the

squelch input is driven to a low state, the CLKOUT pins are

squelched. This is especially useful in repeater applications,

where the recovered clock may not be needed.

I2C INTERFACE

The ADN2817/ADN2818 supports a 2-wire, I2C compatible,

serial bus driving multiple peripherals. Two inputs, serial data

(SDA) and serial clock (SCK), carry information between any

devices connected to the bus. Each slave device is recognized by

a unique address. The ADN2817/ADN2818 has two possible 7-

bit slave addresses for both read and write operations. The MSB

of the 7-bit slave address is factory programmed to 1. B5 of the

slave address is set by Pin 19, SADDR5. Slave address bits [4:0]

are defaulted to all 0s. The slave address consists of the 7 MSBs

of an 8-bit word. The LSB of the word sets either a read or write

operation (see Figure 7). Logic 1 corresponds to a read

operation, while Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must be

followed. First, the master initiates a data transfer by establish-

ing a start condition, defined by a high to low transition on

SDA while SCK remains high. This indicates that an

address/data stream follows. All peripherals respond to the start

condition and shift the next eight bits (the 7-bit address and the

R/W bit). The bits are transferred from MSB to LSB. The

peripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDA and SCK lines

waiting for the start condition and correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on

the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the first

byte means that the master reads information from the

peripheral.

The ADN2817/ADN2818 acts as a standard slave device on the

bus. The data on the SDA pin is 8 bits long supporting the 7-bit

addresses plus the R/W bit. The ADN2817/ADN2818 has 8

subaddresses to enable the user-accessible internal registers (see

Table 1 through Table 7). It, therefore, interprets the first byte as

the device address and the second byte as the starting

subaddress. Autoincrement mode is supported, allowing data to

be read from or written to the starting subaddress and each

subsequent address without manually addressing the

subsequent subaddress. A data transfer is always terminated by

a stop condition. The user can also access any unique

subaddress register on a one-by-one basis without updating all

registers.

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, then they cause an

immediate jump to the idle condition. During a given SCK high

period, the user should issue one start condition, one stop

condition, or a single stop condition followed by a single start

condition. If an invalid subaddress is issued by the user, the

ADN2817/ADN2818 does not issue an acknowledge and

returns to the idle condition. If the user exceeds the highest

subaddress while reading back in autoincrement mode, then the

highest subaddress register contents continue to be output until

the master device issues a no-acknowledge. This indicates the

end of a read. In a no-acknowledge condition, the SDATA line

is not pulled low on the ninth pulse. See Figure 8 and Figure 9

for sample read and write data transfers and Figure 10 for a

more detailed timing diagram.

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2817/ADN2818. However, support for

an optional reference clock is provided. The reference clock can

be driven differentially or single-ended. If the reference clock is

not being used, then REFCLKP should be tied to VCC, and

REFCLKN can be left floating or tied to VEE (the inputs are

internally terminated to VCC/2). See Figure 21 through Figure

23 for sample configurations.

The REFCLK input buffer accepts any differential signal with a

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