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ADN2817 数据表(PDF) 12 Page - Analog Devices |
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ADN2817 数据表(HTML) 12 Page - Analog Devices |
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12 / 35 page  ADN2817/ADN2818 Preliminary Technical Data Rev. PrA | Page 12 of 35 Table 6. Internal Register Map1 Reg Name R/W ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 FREQ0 R0x0 MSB LSB FREQ1 R0x1 MSB LSB FREQ2 R0x2 0 MSB LSB RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1] MISC R 0x4 x x LOS status Static LOL LOL status datarate meas complete x COARSE_RD[0] LSB CTRLA W0x8 FREF Range Data Rate/DIV FREF Ratio Measure Data Rate Lock to Reference CTRLA_RD R 0x5 readback CTRLA CTRLB W 0x9 Config LOL Reset MISC[4] System Reset 0 Reset MISC[2] 00 0 CTRLB_RD R 0x6 readback CTRLB CTRLC W0x11 0 0 Set Signal Degrade Threshold Enable Signal Degrade LOS forces acquisition Config LOS Squelch Mode Boost Output CTRLD W0x22 CDR Bypass Disable DATA Buffer Disable CLK Buffer Initiate PRBS Sequence PRBS Mode[2..0] FDDI_MODE W0x0D FDDI Mode Enable Subharmonic Ratio 0 0 SEL_MODE W 0x34 0 0 Acq Mode Cont Rate / Single Rate Datarate Range CLK Holdover Mode 2A CLK Holdover Mode 2B 0 HI_CODE W 0x35 HI_CODE[8] HI_CODE[1] LO_CODE W 0x36 LO_CODE[8] LO_CODE[1] CODE_LSB W0x39 0 0 0 0 0 0 HI_CODE[0] LO_CODE[0] BERCTLA W 0x1E BER Timer Phase Polarity BER Start Pulse Error Count Byte Select, e.g. 011=Byte 3 of 5 BERCTLB W0x1F 0 0 Enable BER BER Stdby Mode Clock XOR Input BER Mode BERSTS R0x20 x x x x x x x BER Meas Status BER_RES R 0x21 BER_RES[7..0], BER Measurement Result BER_DAC R 0x24 BER_DAC[7..0], Output of BER DAC PHASE W 0x37 PHASE[7..0], 2's Complement Sample Phase Offset Adjustment 1 All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC LOS Status Static LOL LOL Status Datarate Measurement Complete Coarse Rate Readback LSB D7 D6 D5 D4 D3 D2 D1 D0 x x 0 = No loss of signal 0 = Waiting for next LOL 0 = Locked 0 = Measuring datarate x COARSE_RD[0] 1 = Loss of signal 1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete Table 8. Control Register, CTRLA1 FREF Range Datarate/Div_FREF Ratio Measure Datarate Lock to Reference D7 D6 D5 D4 D3 D2 D1 D0 0 0 12.3 MHz to 25 MHz 0 0 0 0 1 Set to 1 to measure datarate 0 = Lock to input data 0 1 25 MHz to 50 MHz 0 0 0 1 2 1 = Lock to reference clock 1 0 50 MHz to 100 MHz 0 0 1 0 4 1 1 100 MHz to 200 MHz n 2n 1 0 0 0 256 1 Where DIV_F REF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section). |
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