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ADN2817 数据表(PDF) 3 Page - Analog Devices

部件名 ADN2817
功能描述  Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
PDF  35 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN2817 数据表(HTML) 3 Page - Analog Devices

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Preliminary Technical Data
ADN2817/ADN2818
Rev.Pr A | Page 3 of 35
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
1.8
2.8
V
Peak-to-Peak Differential Input
PIN – NIN
2.0
V
Input Common Mode Level
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
2.3
2.5
2.8
V
Differential Input Sensitivity
223 − 1 PRBS, ac-coupled,1 BER = 1 x 10–10
TBD
TBD
mV p-p
Input Overdrive
(see Figure 12)
TBD
TBD
mV p-p
Input Offset
TBD
μV
Input RMS Noise
BER = 1 x 10–10
TBD
μV rms
QUANTIZER—AC CHARACTERISTICS
Data Rate
12.3
2700
Mb/s
S11
@ 2.5 GHz
−15
dB
Input Resistance
Differential
100
Ω
Input Capacitance
0.65
pF
QUANTIZER—SLICE ADJUSTMENT
Gain
SLICEP – SLICEN = ±0.5 V
TBD
0.1
TBD
V/V
Differential Control Voltage Input
SLICEP – SLICEN
TBD
V
Control Voltage Range
DC level @ SLICEP or SLICEN
VEE
0.95
V
Slice Threshold Offset
1
mV
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
RThresh = 0 Ω
TBD
TBD
mV
RThresh = 100 kΩ
TBD
TBD
mV
Hysteresis (Electrical)
OC-48
RThresh = 0 Ω
TBD
TBD
dB
RThresh = 100 kΩ
TBD
TBD
dB
OC-1
RThresh = 0 Ω
TBD
TBD
dB
RThresh = 10 kΩ
TBD
TBD
dB
LOS Assert Time
DC-coupled2
TBD
ns
LOS De-Assert Time
DC-coupled2
TBD
ns
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
With respect to nominal
1000
ppm
VCO Frequency Error for LOL De-Assert
With respect to nominal
250
ppm
LOL Response Time
12.3 Mb/s
4
ms
OC-12
1.0
μs
OC-48
1.0
μs
ACQUISITION TIME
Lock to Data Mode
OC-48
1.3
ms
OC-12
2.0
ms
OC-3
3.4
ms
OC-1
9.8
ms
12.3 Mb/s
40.0
ms
Optional Lock to REFCLK Mode
10.0
ms
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2817/ADN2818 input stage.



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